ISL6307BCRZ Intersil, ISL6307BCRZ Datasheet
ISL6307BCRZ
Specifications of ISL6307BCRZ
Available stocks
Related parts for ISL6307BCRZ
ISL6307BCRZ Summary of contents
Page 1
... VID setting. Ordering Information TEMP. PART NUMBER (°C) PACKAGE ISL6307BCRZ (Note 7x7 QFN (Pb-free) L48.7x7 ISL6307BIRZ (Note) - 7x7 QFN (Pb-free) L48.7x7 Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets ...
Page 2
Pinout 1 VID7 2 VID6 3 VID5 4 VID4 5 VID3 6 VID2 7 VID1 8 VID0 9 VRSEL 10 OFS 11 IOUT 12 DAC 2 ISL6307B ISL6307B (48 LD QFN) TOP VIEW ...
Page 3
ISL6307B Block Diagram VDIFF VR_RDY RGND x1 VSEN OVP SOFT-START +200mV FAULT LOGIC SS OFS OFFSET REF DAC VRSEL VID7 VID6 VID5 DYNAMIC VID4 VID D/A VID3 VID2 VID1 VID0 COMP FB 2V OC2 IOUT IDROOP GND 3 ISL6307B VCC ...
Page 4
Typical Application - 6-Phase Buck Converter with R NTC2 EXTERNAL TCOMP COMPENSATION NETWORK FB COMP REF IDROOP DAC VDIFF VSEN VCC RGND GND VTT EN_VTT VR_RDY ISL6307B VID7 PWM6 VID6 ISEN6- VID5 ISEN6+ VID4 PWM4 VID3 ISEN4- VID2 ISEN4+ VID1 ...
Page 5
Typical Application - 6-Phase Buck Converter with R FB COMP REF IDROOP DAC VDIFF VSEN VCC RGND GND VTT EN_VTT VR_RDY ISL6307B VID7 PWM6 VID6 ISEN6- VID5 ISEN6+ VID4 PWM4 VID3 ISEN4- VID2 ISEN4+ VID1 VID0 PWM2 VRSEL ISEN2- OVP ...
Page 6
Typical Application - 6-Phase Buck Converter with DCR Sensing and External TCOMP NTC2 EXTERNAL TCOMP COMPENSATION NETWORK FB COMP REF IDROOP DAC VDIFF VSEN VCC RGND GND VTT EN_VTT VR_RDY ISL6307B VID7 PWM6 VID6 ISEN6- VID5 ISEN6+ VID4 PWM4 VID3 ...
Page 7
Typical Application - 6-Phase Buck Converter with DCR Sensing and Integrated TCOMP +12V FB COMP REF IDROOP DAC VDIFF VSEN VCC RGND GND VTT EN_VTT VR_RDY ISL6307B VID7 PWM6 VID6 ISEN6- VID5 ISEN6+ VID4 PWM4 VID3 ISEN4- VID2 ISEN4+ VID1 ...
Page 8
... ESD (Charged device model . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV Operating Conditions Voltage at VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Ambient Temperature (ISL6307BCRZ 0°C to 70°C Ambient Temperature (ISL6307BIRZ .-40°C to 85°C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied ...
Page 9
... Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA (Note 3). Unless Otherwise Specified (Continued) PARAMETER PIN-ADJUSTABLE OFFSET Voltage at OFS Pin for ISL6307BCRZ Voltage at OFS Pin for ISL6307BIRZ OSCILLATORS Accuracy of Switching Frequency Setting Adjustment Range of Switching Frequency (Note 4) Soft-start Ramp Rate (Notes 5, 6) ...
Page 10
Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA (Note 3). Unless Otherwise Specified (Continued) PARAMETER VR-RDY Reset Voltage Overvoltage Protection Threshold Overvoltage Reset Threshold OVP Output High Voltage OVP Output Low Voltage NOTES: 3. These parts are ...
Page 11
... PWM1, PWM2, PWM3, PWM4, PWM5, PWM6 - Pulse- width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver IC. The number of active channels is determined by the state of PWM3, PWM4, PWM5 and PWM 6. Tie PWM3 to VCC to configure for 2-phase operation. Tie PWM4 to VCC to configure for 3-phase operation ...
Page 12
IL1 + IL2 + IL3, 7A/DIV IL3, 7A/DIV PWM3, 5V/DIV PWM2, 5V/DIV IL1, 7A/DIV PWM1, 5V/DIV 1µs/DIV FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 3-PHASE CONVERTER Interleaving The switching of each channel in a multiphase converter is timed to be ...
Page 13
PWM Operation The timing of each converter leg is set by the number of active channels. The default channel setting for the ISL6307B is four. One switching cycle is defined as the time between PWM1 pulse termination signals. The pulse ...
Page 14
ISL6612 INDUCTOR R PWM(n) ISL6307B INTERNAL CIRCUIT I n SAMPLE & ISEN-(n) HOLD + - ISEN+(n) DCR I I ------------------- = SEN L R ISEN FIGURE 4. DCR SENSING CONFIGURATION With the internal low-offset current amplifier, the ...
Page 15
... The output of the error amplifier, V COMP sawtooth waveform to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference 15 ISL6307B voltage. The internal and external circuitry which control voltage regulation is illustrated in Figure 8 ...
Page 16
TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION) VID4 VID3 VID2 VID1 VID0 VID5 400mV 200mV 100mV 50mV 25mV 12.5mV ...
Page 17
TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION) VID4 VID3 VID2 VID1 VID0 VID5 400mV 200mV 100mV 50mV 25mV 12.5mV ...
Page 18
TABLE 2. VR11 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...
Page 19
TABLE 2. VR11 VID 8-BIT (Continued) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE ...
Page 20
The magnitude of the spike is dictated by the ESR and ESL of the output capacitors selected. By positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. ...
Page 21
... ICs reach their POR level before the ISL6307B becomes enabled. The schematic in Figure 10 (EQ. 13) demonstrates sequencing the ISL6307B with the ISL66xx family of Intersil MOSFET drivers, which require 12V bias. 3. The voltage on EN_VTT must be higher than 0.875V to enable the controller. This pin is typically connected to the output of VTT VR ...
Page 22
... At the inception of an overvoltage event, all PWM outputs are commanded low instantly (less than 20ns) until the voltage at VDIFF falls below 0.4V. This causes the Intersil drivers to turn on the lower MOSFETs and pull the output voltage below a level that might cause damage to the load. ...
Page 23
... SW At the beginning of overcurrent shutdown, the controller places all PWM signals in a high-impedance state within 20ns commanding the Intersil MOSFET driver ICs to turn off both upper and lower MOSFETs. The system remains in this state a period of 4096 switching cycles. If the controller is still enabled at the end of this wait period, it will attempt a soft- start ...
Page 24
V_IOUT, 200mV/DIV 0A 50A FIGURE 14. VOLTAGE AT IOUT PIN WITH A NTC NETWORK PLACED BETWEEN IOUT TO GROUND WHEN LOAD CURRENT CHANGES Thermal monitoring (VR_HOT/VR_FAN) There are two thermal signals to indicate the temperature status of the voltage regulator: ...
Page 25
Based on the NTC temperature characteristics and the desired threshold of VR_HOT signal, the pull-up resistor RTM1 of TM pin is given by 2.75xR ( ) TM1 NTC the NTC resistance at the VR_HOT threshold ...
Page 26
... It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications ...
Page 27
In cases where board space is the limiting constraint, current can be pushed as high as 40A per phase, but these designs require heat sinks and forced air to cool the MOSFETs, inductors ...
Page 28
---------- ISEN 2 , ISEN ∆ Equation 31, make sure that ∆T is the desired temperature ...
Page 29
COMP IDROOP VDIFF FIGURE 21. COMPENSATION CIRCUIT FOR ISL6307B BASED CONVERTER WITHOUT LOAD-LINE REGULATION In Equation 34 the per-channel filter inductance divided by the number ...
Page 30
ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output- voltage deviation is less than the allowable maximum. Neglecting the ...
Page 31
0.5 I L,P-P L,P 0. 0.75 I L,P-P O L,P-P 0.2 0 0.2 0.4 0.6 DUTY CYCLE (V O/ FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs DUTY ...
Page 32
... Align the output inductors and MOSFETs such that spaces between the components are minimized while creating the PHASE plane. Place the Intersil MOSFET driver IC as close as possible to the MOSFETs they control to reduce the parasitic impedances due to trace length between critical driver input and output signals ...
Page 33
... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...