ISL6326CRZ-T Intersil, ISL6326CRZ-T Datasheet - Page 13

• Manufacturer Part Number: ISL6326CRZ-T
• Description: IC CTRLR PWM 4PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6326CRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 25%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RESISTIVE SENSING
For accurate current sense, a dedicated current-sense
resistor R
serve as the current sense element (see Figure 4). This
technique is more accurate, but reduces overall converter
efficiency due to the additional power loss on the current
sense element R
The same capacitor C
between ISEN- and ISEN+ signals. Select the proper C
keep the time constant of R
to 27ns.
Equation 7 shows the ratio of the channel current to the
sensed current I
The inductor DCR value will increase as the temperature
increases. Therefore the sensed current will increase as the
temperature of the current sense element increases. In order
to compensate the temperature effect on the sensed current
signal, a Positive Temperature Coefficient (PTC) resistor can
be selected for the sense resistor R
temperature compensation function of ISL6326 should be
utilized. The integrated temperature compensation function
is described in “Temperature Compensation” on page 22.
Channel-Current Balance
The sensed current I
together and divided by the number of active channels. The
resulting average current (I
total load current. Channel current balance is achieved by
comparing the sensed current of each channel to the
average current to make an appropriate adjustment to the
PWM duty cycle of each channel with Intersil’s patented
current-balance method.
Channel current balance is essential in achieving the
thermal advantage of multiphase operation. With good
I
SEN
FIGURE 4. SENSE RESISTOR IN SERIES WITH INDUCTORS
=
ISL6326 INTERNAL CIRCUIT
I
L
CURRENT
SENSE
⋅
SENSE
I
R
-----------------------
SEN
R
SENSE
I
n
ISEN
=
SEN
SENSE
in series with each output inductor can
I
L
R SENSE
------------------------- -
.
n
R ISEN
T
from each active channel is summed
.
is needed to match the time delay
+
-
AVG
ISEN
13
) provides a measure of the
ISEN-(n)
ISEN+(n)
L
and C
ISEN
T
R
I L
SENSE
, or the integrated
(R
ISEN
R
C
ISEN(n)
T
C
V
OUT
x C
OUT
T
) close
(EQ. 7)
T
to
ISL6326
current balance, the power loss is equally dissipated over
multiple devices and a greater area.
Voltage Regulation
The compensation network shown in Figure 5 assures that
the steady-state error in the output voltage is limited only to
the error in the reference voltage (output of the DAC) and
offset errors in the OFS current source, remote-sense and
error amplifiers. Intersil specifies the guaranteed tolerance of
the ISL6326 to include the combined tolerances of each of
these elements.
The output of the error amplifier (V
sawtooth waveforms to generate the PWM signals. The
PWM signals control the timing of the Intersil MOSFET
drivers and regulate the converter output to the specified
reference voltage. The internal and external circuitry, which
control voltage regulation are illustrated in Figure 5.
The ISL6326 incorporates an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground
reference point resulting in a more accurate means of
sensing output voltage. Connect the microprocessor sense
pins to the non-inverting input (VSEN) and inverting input
(RGND) of the remote-sense amplifier. The remote-sense
output (V
amplifier through an external resistor.
A digital-to-analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID7
through VID0. The DAC decodes the eight 6-bit logic signal
(VID) into one of the discrete voltages shown in Table 1.
Each VID input offers a 45µA pull-up to an internal 2.5V
source for use with open-drain outputs. The pull-up current
FIGURE 5. OUTPUT VOLTAGE AND LOAD-LINE
R
FB
EXTERNAL CIRCUIT
V
V
DIFF
OUT
OUT
+
-
V
DROOP
C
R
REF
-
+
C
REGULATION WITH OFFSET ADJUSTMENT
) is connected to the inverting input of the error
R
C
REF
C
IDROOP
RGND
COMP
VDIFF
VSEN
DAC
REF
FB
ISL6326 INTERNAL CIRCUIT
I
AVG
COMP
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
ERROR AMPLIFIER
+
-
) is compared to
+
-
V
COMP
May 5, 2008
FN9262.1