ISL8120IRZ-T Intersil, ISL8120IRZ-T Datasheet - Page 23
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ISL8120IRZ-T
Manufacturer Part Number
ISL8120IRZ-T
Description
IC CTRLR PWM 2/NPHASE 32-QFN
Manufacturer
Intersil
Datasheet
1.ISL8120IRZ-T.pdf
(33 pages)
Specifications of ISL8120IRZ-T
Pwm Type
Voltage Mode
Number Of Outputs
2
Frequency - Max
1.5MHz
Duty Cycle
90%
Voltage - Supply
3 V ~ 22 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Frequency-max
1.5MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL8120IRZ-T
Manufacturer:
INTERSIL
Quantity:
20 000
While EN/FF is pulled to ground, a constant voltage (0.8V) is
fed into the ramp generator to maintain a minimum
peak-to-peak ramp.
Since the EN/FF pins are pulled down under fault conditions,
the pull-up resistor (R
than 5mA current from EN/FF pin. Essentially, the EN/FF
pins cannot be directly connected to VCC.
Soft-start
The ISL8120IRZEC has two independent digital pre-charged
soft-start circuitry, which has a rise time inversely
proportional to the switching frequency and is determined by
an digital counter that increments with every pulse of the
phase clock. Refer to Figure 7. The full soft-start time from
0V to 0.6V can be estimated by Equation 1.
The ISL8120IRZEC has the ability to work under a
pre-charged output (see Figure 8). The output voltage would
not be yanked down during pre-charged start-up. If the pre-
charged output voltage is greater than the final target level
but prior to 113% setpoint, the switching will not start until the
output voltage reduces to the target voltage and the first
PWM pulse is generated (see Figure 9). The maximum
allowable pre-charged level is 113%. If the pre-charged level
is above 113% but below 120%, the output will hiccup
between 113% (LGATE turns on) and 87% (LGATE turns off)
while EN/FF is pulled low. If the pre-charged load voltage is
above 120% of the targeted output voltage, then the
controller will be latched off and not be able to power-up.
See “PRE-POR Overvoltage Protection (PRE-POR-OVP)”
on page 24 for details.
For above target pre-charged start-up, the output voltage
would not change until the end of the soft-start. If the initial
dip is below the UV level, the LGATE could be turned off. In
such an event, the body-diode drop of the low-side FET will
be sensed and could potentiality cause an OCP event for
r
t
SS
DS(ON)
R
FIGURE 6. TYPICAL 4-PHASE WITH FAULT HANDSHAKE
UP
=
1280
------------ -
f
=
SW
current sensing applications.
--------------------------------------------------------- -
I
EN_HYS
ISL8120IRZEC
V
2-PHASE
EN_HYS
⋅
EN/FF1
EN/FF2
N
PHASE
UP
) should be scaled to sink no more
23
VIN
R
R
UP
DOWN
EN/FF1
EN/FF2
ISL8120IRZEC
2-PHASE
(EQ. 1)
ISL8120IRZEC
Power-Good
FIGURE 9. SOFT-START WITH VOUT BELOW OV BUT
CHANNEL 2 UV/OV
CHANNEL 1 UV/OV
END OF SS2
END OF SS1
-100mV
FIGURE 10. POWER-GOOD THRESHOLD WINDOW
-100mV
FIRST PWM PULSE
UV
FIGURE 8. SOFT-START WITH VOUT = UV
FIGURE 7. SOFT-START WITH VOUT = 0V
0.0V
UV
FIRST PWM PULSE
ABOVE FINAL TARGET VOLTAGE
GOOD
FIRST PWM PULSE
OR
PRE-OV (NO LATCH)
VMON1, 2
AND
t
SS_DLY
SS SETTLING AT VREF + 100mV
SS SETTLING AT VREF + 100mV
VOUT TARGET VOLTAGE
VOUT
≈
GOOD
t
----------- -
F
SS
384
SW
=
UV
VOUT
OV = 113%
1280
------------ -
< +20%
F
V
REF
SW
April 21, 2009
PGOOD
+13%
+9%
-9%
-13%
+20%
FN6763.1