ISL6560CBZ-T Intersil, ISL6560CBZ-T Datasheet - Page 11

• Manufacturer Part Number: ISL6560CBZ-T
• Description: IC CORE VOLTAGE REG PWM 16-SOIC
• Manufacturer: Intersil

Specifications of ISL6560CBZ-T

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 50%
• Voltage - Supply: 3 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 2MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the following
equations). The conduction losses are the main component
of power dissipation for the lower MOSFETs, Q2 and Q4 of
Figure 10. Only the upper MOSFETs, Q1 and Q3 have
significant switching losses, since the lower device turns on
and off into near-zero voltage.
The equations assume linear voltage-current transitions and
do not model power loss due to the reverse-recovery of the
lower MOSFET’s body diode. The gate-charge losses are
dissipated by the driver IC and don't heat the MOSFETs.
However, large gate-charge increases the switching time,
t
PC Board Layout Considerations
Like all high-current supplies where low-voltage control
signals in the millivolt range must live with high voltage and
high-current switching signals, PC board layout becomes
crucial in obtaining a satisfactory supply.
Figure 11 shows a simplified diagram of the critical areas of
a PC board layout. This diagram and the following material
represent goals to work towards during the layout phase.
Goals will be compromised during the layout process due to
SW
which increases the upper MOSFET switching losses.
R27
R12
R11
22k
4.3k
15k
FIGURE 10. SCHEMATIC DIAGRAM OF A 40A SUPPLY USING THE ISL6560 CONTROLLER AND HIP6601 GATE DRIVERS
1nF
VID CODES
PROCSSOR
+V
C15, C17-18, C29, C50-51
INPUT
IN
from
C12
12V
1k
R5
6 - 470µF
1µH
L3
{
{
150pF
100pF
1
2
3
4
5
6
7
8
C13
VID4
VID3
VID2
VID1
VID0
COMP
FB
CT
C14
11
ISL6560
PWRGD
PWM1
PWM2
2 - 4.7µF
C41-42
GND
VCC
REF
CS+
CS-
16
15
14
13
12
11
10
9
4.7µF
C40
10Ω
R6
1nF
C10
15nF
330Ω
5mΩ
R13
C20
R7
330pF
C11
ISL6560
20Ω
R14
1
2
3
4
1
2
3
4
UGATE
BOOT
PWM
GND
UGATE
BOOT
PWM
GND
HIP6601ECB
HIP6601ECB
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications. A separate heat sink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Figure 10 shows a schematic of the circuit developed from
the proceeding computations. This circuit is implemented on
the ISL6560/62 Evaluation Board. The next section will
discuss PC board layout.
component placement and space constraints. The following
text reviews these layout considerations in more detail.
Current Sampling
P
P
1. Place the current sampling or sense resistor as close as
UPPER
LOWER
possible to the upper MOSFET drains. This is important
since the added inductance and resistance increase the
impedance and result in a reduction in drain voltage
during high peak pulse currents.
PHASE
PHASE
LGATE
LGATE
PVCC
PVCC
VCC
VCC
=
=
C2
1µF
8
7
6
5
8
7
6
5
I
----------------------------------------------------------- -
1µF
I
-------------------------------------------------------------------------------- -
O
O
2
2
×
×
C4
r
r
DS ON
DS ON
0.1µF
0.1µF
C1
C3
V
(
(
IN
)
V
)
×
×
IN
Q2 HUF76145
Q1 HUF76139
Q4
V
Q3
HUF76139
(
HUF76145
V
OUT
IN
900nH
900nH
–
L1
L2
+
V
I
----------------------------------------------------
OUT
O
×
V
)
C39, C45-49,
IN
C21, C24-28
6 - 1200µF
16 - 22µF
C19, C30,
C34-37,
C60-63
×
2
t
SW
×
F
S
+V
FN9011.3
CORE