ISL6565ACV Intersil, ISL6565ACV Datasheet
![no-image](/images/manufacturer_photos/0/3/341/intersil_sml.jpg)
ISL6565ACV
Specifications of ISL6565ACV
Available stocks
Related parts for ISL6565ACV
ISL6565ACV Summary of contents
Page 1
... VID setting. Ordering Information PART NUMBER PART MARKING ISL6565ACB ISL6565ACB ISL6565ACBZ (Note) ISL6565ACBZ ISL6565ACR ISL6565ACR ISL6565ACRZ (Note) ISL6565ACRZ ISL6565ACV ISL6565ACV ISL6565ACVZ (Note) ISL6565ACVZ ISL6565BCB ISL6565BCB ISL6565BCBZ (Note) ISL6565BCBZ ISL6565BCR ISL6565BCR ISL6565BCRZ (Note) ISL6565BCRZ ISL6565BCV ISL6565BCV ISL6565BCVZ (Note) ISL6565BCVZ *Add " ...
Page 2
... Pinouts ISL6565ACB (SOIC), ISL6565ACV (TSSOP) TOP VIEW OVP 1 PGOOD 2 VID4 3 VID3 4 VID2 5 VID1 6 VID0 7 8 VID12.5 OFS 9 10 TCOMP 11 REF 12 FB COMP 13 14 VDIFF ISL6565BCB (SOIC), ISL6565BCV (TSSOP) TOP VIEW OVP 1 PGOOD 2 VID4 3 VID3 4 VID2 5 VID1 6 VID0 7 8 VID12.5 OFS 9 TCOMP ...
Page 3
ISL6565A Block Diagram PGOOD VDIFF RGND x1 VSEN UVP OVP +200mV x 0.75 VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 REF FB COMP ∑ OFS OFFSET TEMP TCOMP COMP 3 ISL6565A, ISL6565B OVP VCC OVP S R SHUNT ...
Page 4
ISL6565B Block Diagram PGOOD VDIFF RGND x1 VSEN UVP OVP +200mV x 0.75 VID4 VID3 DYNAMIC VID2 VID VID1 D/A VID0 VID12.5 REF FB COMP ∑ OFS OFFSET TEMP TCOMP COMP 4 ISL6565A, ISL6565B OVP VCC OVP R S SHUNT ...
Page 5
Typical Application - ISL6565A +5V FB COMP VCC VDIFF TCOMP VSEN RGND PGOOD REF OVP ISL6565A VID4 PWM1 ISEN1 VID3 VID2 PWM2 VID1 ISEN2 VID0 PWM3 VID12.5 ISEN3 OFS GND ENLL R T +12V VID_PGOOD 5 ISL6565A, ...
Page 6
Typical Application - ISL6565B +5V COMP VCC FB VDIFF TCOMP VSEN RGND PGOOD REF OVP ISL6565B VID4 PWM1 ISEN1 VID3 VID2 PWM2 VID1 ISEN2 VID0 PWM3 VID12.5 ISEN3 ICOMMON OFS FS EN GND ENLL R T +12V VID_PGOOD 6 ISL6565A, ...
Page 7
Absolute Maximum Ratings Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V ...
Page 8
Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA (Note 4), T Unless Otherwise Specified. (Continued) PARAMETER OSCILLATOR Accuracy Adjustment Range Sawtooth Amplitude Max Duty Cycle ERROR AMPLIFIER Open-Loop Gain (Note 7) Open-Loop Bandwidth (Note 7) Slew Rate ...
Page 9
... FB pin, adjusting for MOSFET r variations with temperature. PWM1, PWM2, PWM3 - Pulse-width modulation outputs. Connect these pins to the PWM input pins of the Intersil driver ICs. The number of active channels is determined by the state of PWM3. Tie PWM3 to VCC to configure for 2-phase operation. ...
Page 10
Operation Multi-Phase Power Conversion Microprocessor load current profiles have changed to the point that the advantages of multi-phase power conversion are impossible to ignore. The technical challenges associated with producing a single-phase converter that is both cost-effective and thermally viable ...
Page 11
Figures 19 and 20 in the section entitled Input Capacitor Selection can be used to determine the input-capacitor RMS current based on load current, duty cycle, and the number of channels. They are provided as aids in determining the optimal ...
Page 12
... Intersil’s patented current-balance method is illustrated in Figure 6, with error correction for channel 1 represented. In the figure, the cycle average current combines with the ...
Page 13
... The output of the error amplifier, V COMP sawtooth waveform to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The internal and external circuitry that controls voltage regulation is illustrated in Figure 7. ...
Page 14
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES VID4 VID3 VID2 VID1 VID0 ...
Page 15
As shown in Figure 7, a current proportional to the average current in all active channels flows from FB through a AVG load-line regulation resistor The resulting voltage drop FB across R is proportional to the ...
Page 16
The ISL6565A, ISL6565B checks the VID inputs six times every switching cycle. If the VID code is found to have changed, the controller waits half of a complete cycle before executing a 12.5mV change. If during the half-cycle wait period, ...
Page 17
... ICs reach their POR level before the ISL6565A, ISL6565B becomes enabled. The schematic in Figure 11 demonstrates sequencing the ISL6565A, ISL6565B with the HIP660X family of Intersil MOSFET drivers, which require 12V bias. 3. The voltage on ENLL must be logic high to enable the controller ...
Page 18
... VCC or 1.5V otherwise. This causes the + I 1 Intersil drivers to turn on the lower MOSFETs and pull the REPEAT FOR output voltage below a level that might cause damage to the EACH CHANNEL load. The PWM outputs remain low until VDIFF falls to the programmed DAC level at which time they enter a high- 110µ ...
Page 19
... At the beginning of overcurrent shutdown, the controller places all PWM signals in a high-impedance state commanding the Intersil MOSFET driver ICs to turn off both upper and lower MOSFETs. The system remains in this state for a period of 4096 switching cycles. If the controller is still enabled at the end of this wait period, it will attempt a soft- start (as shown in Figure 14) ...
Page 20
P ≈ f ---- ----- - + -------- - ...
Page 21
ISL6605 INDUCTOR PWM(n) ISL6565B ISEN(n) ICOMMON FIGURE 16. DCR SENSING CONFIGURATION The time constant of this R-C network must match the time constant of the inductor L/DCR. Follow the steps below to choose the ...
Page 22
Equations 33 and 34 the resistor divider ratio of the corresponding phase RC network is being changed. In the phase being adjusted, this new ratio, K (described in Equation 35), can not exceed 1.0. ...
Page 23
C (OPTIONAL COMP DROOP - VDIFF FIGURE 17. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6565A, ISL6565B CIRCUIT Since the system poles and zero are affected by the values of the components ...
Page 24
ESL and ESR so that the total output- voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount di ∆V ≈ ( ...
Page 25
L, 0 0. 0.2 0.4 0.6 DUTY CYCLE (V IN/ FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR 2-PHASE CONVERTER For a two-phase ...
Page 26
... Nominal dimensions are provided to assist with PCB Land Pattern C L Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when L Anvil singulation method is used and not present for saw ...
Page 27
Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...
Page 28
... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...