ISL8102IRZ-T Intersil, ISL8102IRZ-T Datasheet
ISL8102IRZ-T
Specifications of ISL8102IRZ-T
Related parts for ISL8102IRZ-T
ISL8102IRZ-T Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL8102 FN9247 ...
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... Ordering Information PART NUMBER PART MARKING ISL8102CRZ (Note) * ISL8102 CRZ ISL8102IRZ (Note) * ISL8102 IRZ ISL8102EVAL1 Evaluation Platform * Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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Block Diagram ICOMP DROOP ISEN AMP ISUM IREF RGND VSEN x1 x1 VDIFF UVP OVP OVP +150mV x 0.82 REF1 DAC REF0 DAC REF E/A FB COMP OFST OFFSET 3 ISL8102 OCSET PGOOD OVP 100µA OC +1V SOFT-START AND FAULT ...
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Typical Application - ISL8102 FB VDIFF VSEN RGND +5V 2PH VCC OFST FS DAC ISL8102 REF REF1 REF0 OVP PGOOD +12V GND ENLL IREF DROOP ICOMP OCSET 4 ISL8102 +12V COMP PVCC BOOT1 UGATE1 PHASE1 ISEN1 LGATE1 +12V BOOT2 UGATE2 ...
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... PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature (ISL8102CR, ISL8102CRZ 0°C to +70°C Ambient Temperature (ISL8102IR, ISL8102IRZ .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER ERROR AMPLIFIER DC Gain (Note 3) ...
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Timing Diagram t PDHUGATE UGATE LGATE t FLGATE Simplified Power System Diagram +12V IN + REF0,REF1 ENLL OVP PGOOD Functional Pin Description VCC (Pin 3) Bias supply for the IC’s small-signal circuitry. Connect this pin to a +5V ...
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Table 1 on page 11 for correspondence between REF0 and REF1 inputs and reference voltage settings. These pins are internally pulled high, to approximately 1.2V, by 40µA (typically) internal current sources; the internal ...
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PGOOD (Pin 28) PGOOD is used as an indication of the end of soft-start open-drain logic output that is low impedance until the soft-start is completed and ...
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... Channel current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. Intersil’s patented current balance method is illustrated in Figure 3, with error correction for Channel 1 represented. In the figure, the cycle ...
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During this time the current sense amplifier uses the ISEN inputs to reproduce a signal proportional to the inductor current This sensed current scaled version of the inductor current. The sample window opens ...
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... DAC or the external voltage reference) and offset errors in the OFS current source, remote sense and error amplifiers. Intersil specifies the guaranteed tolerance of the ISL8102 to include the combined tolerances of each of these elements, except when an external reference or voltage divider is used, then the tolerances of these components has to be taken into account ...
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If the R-C network components are selected such that the R-C time constant matches the inductor L/DCR time constant, then V is equal to the sum of the voltage DROOP drops across the individual DCRs, multiplied by a gain. As ...
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Advanced Adaptive Zero Shoot-Through Deadtime Control (Patent Pending) The integrated drivers incorporate a unique adaptive deadtime control technique to minimize deadtime, resulting in high efficiency from the reduced freewheeling time of the lower MOSFET body-diode conduction, and to prevent the ...
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ISL8102 INTERNAL CIRCUIT POR CIRCUIT ENABLE COMPARATOR + - 0.66V SOFT-START AND FAULT LOGIC FIGURE 11. POWER SEQUENCING USING THRESHOLD- SENSITIVE ENABLE (ENLL) FUNCTION 2. The voltage on ENLL must be above 0.66V. The EN input allows for power sequencing ...
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DROOP to IREF to disable the Droop feature R OCSET DROOP* - ICOMP V OCSET IREF + ISEN - - V DROOP ISUM + OC + VDIFF - +1V DAC + 150mV SOFT-START, FAULT AND CONTROL LOGIC V OVP ...
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... It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for many applications. ...
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When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET ...
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BOOT PVCC HI1 UGATE R R LO1 R G1 PHASE FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH PVCC HI2 LGATE LO2 GI2 G2 FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH ...
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PHASE1 R S PHASE2 R S ISUM R C COMP COMP ICOMP - DROOP V DROOP IREF + ISL8102 FIGURE 18. DCR SENSING CONFIGURATION Due to errors in the inductance or DCR it may be necessary to adjust the value ...
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ESR zero of the voltage mode approximation, yields a solution that is always stable with very close to ideal transient performance. The feedback resistor has already been chosen as 1 outlined in “Load Line Regulation ...
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COMP - FB + E/A VREF VDIFF - RGND + VSEN OSCILLATOR V OSC PWM CIRCUIT UGATE HALF-BRIDGE DRIVE PHASE LGATE ISL8102 EXTERNAL CIRCUIT FIGURE 22. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN The compensation network ...
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F against the capabilities of the error P2 amplifier. The closed loop gain constructed on the CL log-log graph of Figure 23 by adding the modulator gain, G (in dB), to the feedback compensation ...
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Switching Frequency There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper MOSFET loss calculation. These effects are outlined in “MOSFETs” on page 17, and they establish the upper ...
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Consider example, the turnoff transition of the upper PWM MOSFET. Prior to turnoff, the upper MOSFET was carrying channel current. During the turnoff, current stops flowing in the upper MOSFET and is picked up ...
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VDIFF VSEN RGND +5V 2PH VCC C HF0 R OFST OFST DAC ISL8102 R REF REF C REF REF1 REF0 OVP PGOOD +12V GND ENLL IREF DROOP OCSET ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...