ISL6422EVEZ Intersil, ISL6422EVEZ Datasheet - Page 12

• Manufacturer Part Number: ISL6422EVEZ
• Description: IC VREG DUAL LNB W/I2C 38EPTSSOP
• Manufacturer: Intersil

Specifications of ISL6422EVEZ

• Applications: Converter, Satellite Set-Top Box Designs
• Voltage - Input: 8 ~ 14 V
• Number Of Outputs: 2
• Voltage - Output: 13.3 ~ 18.3 V, 14.3 ~ 19.3 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-TSSOP Exposed Pad, 38-eTSSOP, 38-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can change only when the clock signal on the SCL line is
LOW. Refer to Figure 4.
START and STOP Conditions
As shown in Figure 5, the START condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (see
Figure 6). The peripheral that acknowledges has to pull
down (LOW) the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during this clock
pulse. (Set-up and hold times must also be taken into
account).
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
SDA
SCL
SDA
SCL
CONDITION
START
S
FIGURE 5. START AND STOP WAVEFORMS
DATA VALID
DATA LINE
STABLE
FIGURE 4. DATA VALIDITY
ALLOWED
CHANGE
OF DATA
12
CONDITION
STOP
P
ISL6422
START
SDA
SCL
The ISL6422 will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock pulse without checking the slave acknowledging and
sends the new data. Although, this approach is less
protected from error and decreases the noise immunity.
ISL6422 Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown in Table 2:
• Start condition (S)
• Chip address byte (MSB on left; the LSB bit determines
• Sequence of data (1 byte + Acknowledge)
• Stop condition (P)
System Register Format
• R, W = Read and Write bit
• R = Read-only bit
• X = Unused
All bits reset to 0 at Power-On
SR3H SR3M SR3L
S 0 0 0 1 0 0 0 R/W ACK
R, W
SR1H SR1M
SR2H
R, W
R, W
read (1) or write (0) transmission) (the assigned I
address for the ISL6422 is 0001 00XX)
R, W
FIGURE 6. ACKNOWLEDGE ON THE I
SR2M
R, W
R, W
TABLE 5. COMMAND REGISTER 3 (SR3)
TABLE 3. STATUS REGISTER 1 (SR1)
MSB
TABLE 4. TONE REGISTER 2 (SR2)
TABLE 2. INTERFACE PROTOCOL
1
R, W
SR1L
SR2L
R, W
R, W
DCL1 VSPEN1 ISEL1R
R, W
ENT1
R, W
OTF
R
2
R, W
CABF1 OUVF1 OLF1
MSEL1 TTH1
R, W
R
Data (8 bits)
R, W
8
R, W
X
R
2
ISEL1H ISEL1L
C BUS
ACKNOWLEDGE
R, W
R, W
FROM SLAVE
R
X
August 10, 2007
2
C slave
ACK P
9
FN9190.2
BCF1
R, W
R, W
R
X