ISL6312ACRZ Intersil, ISL6312ACRZ Datasheet - Page 26
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ISL6312ACRZ
Manufacturer Part Number
ISL6312ACRZ
Description
IC CTRLR PWM 4PHASE BUCK 48-QFN
Manufacturer
Intersil
Datasheet
1.ISL6312ACRZ.pdf
(35 pages)
Specifications of ISL6312ACRZ
Applications
Controller, Intel VR10, VR11, AMD CPU
Voltage - Input
5 ~ 12 V
Number Of Outputs
1
Voltage - Output
0.38 ~ 1.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISL6312ACRZ
Manufacturer:
INTERSIL
Quantity:
120
Company:
Part Number:
ISL6312ACRZ-T
Manufacturer:
ANAREN
Quantity:
44
Part Number:
ISL6312ACRZ-T
Manufacturer:
INTERSIL
Quantity:
20 000
Individual Channel Overcurrent Limiting
The ISL6312A has the ability to limit the current in each
individual channel without shutting down the entire regulator.
This is accomplished by continuously comparing the sensed
currents of each channel with a constant 170µA OCL reference
current as shown in Figure 14. If a channel’s individual sensed
current exceeds this OCL limit, the UGATE signal of that
channel is immediately forced low, and the LGATE signal is
forced high. This turns off the upper MOSFET(s), turns on the
lower MOSFET(s), and stops the rise of current in that channel,
forcing the current in the channel to decrease. That channel’s
UGATE signal will not be able to return high until the sensed
channel current falls back below the 170µA reference.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and example
board layouts for all common microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination depends
heavily on the cost analysis which in turn depends on system
constraints that differ from one design to the next. Principally,
the designer will be concerned with whether components can
be mounted on both sides of the circuit board, whether
through-hole components are permitted, the total board space
available for power-supply circuitry, and the maximum amount
of load current. Generally speaking, the most economical
solutions are those in which each phase handles between 25A
and 30A. All surface-mount designs will tend toward the lower
end of this current range. If through-hole MOSFETs and
inductors can be used, higher per-phase currents are possible.
In cases where board space is the limiting constraint, current
can be pushed as high as 40A per phase, but these designs
require heat sinks and forced air to cool the MOSFETs,
inductors and heat-dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is simple,
since virtually all of the loss in the lower MOSFET is due to
current conducted through the channel resistance (r
Equation 24, I
is the peak-to-peak inductor current (see Equation 1), and d is
the duty cycle (V
M
is the maximum continuous output current, I
OUT
/V
IN
).
26
DS(ON)
). In
PP
ISL6312A
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the dead
time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
f
and the end of the lower-MOSFET conduction interval
respectively.
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P
UPPER MOSFET POWER CALCULATION
In addition to r
upper-MOSFET losses are due to currents conducted across
the input voltage (V
higher portion of the upper-MOSFET losses are dependent on
switching frequency, the power calculation is more complex.
Upper MOSFET losses can be divided into separate
components involving the upper-MOSFET switching times,
the lower-MOSFET body-diode reverse-recovery charge, Q
and the upper MOSFET r
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 26,
the required time for this commutation is t
approximated associated power loss is P
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t
approximate power loss is P
A third component involves the lower MOSFET
reverse-recovery charge, Q
fully commutated to the upper MOSFET before the lower-
MOSFET body diode can recover all of Q
through the upper MOSFET across VIN. The power
dissipated as a result is P
Finally, the resistive part of the upper MOSFET is given in
Equation 29 as P
P
P
P
P
P
P
S
LOW 2
UP 1 ,
UP 2 ,
UP 3 ,
UP 4 ,
LOW 1
, and the length of dead times, t
,
,
≈
≈
≈
=
V
r
V
=
DS ON
V
=
IN
IN
V
IN
r
(
D ON
⋅
DS ON
⋅
⎛
⎝
⋅
(
⎛
⎜
⎝
I
----- -
Q
DS(ON)
N
I
----- -
M
N
(
M
)
rr
⋅
+
)
–
d
⋅
UP,4
⋅
I
-------- -
)
I
-------- -
f
⋅
f
PP
PP
IN
2
⋅
S
2
S
⎛
⎜
⎝
⋅
) during switching. Since a substantially
⎞
⎠
⎛
⎜
⎝
⎞
⎟
⎠
:.
I
----- -
losses, a large portion of the
N
I
----- -
M
N
⋅
M
⎛
⎜
⎝
⋅
I
------
⎞
⎟
⎠
⎛
⎜
⎝
⎛
⎜
⎝
N
⎞
⎟
⎠
M
M
2
DS(ON)
t
----
t
----
2
2
2
2
1
UP,3
, V
+
+
⎞
⎟
⎠
⋅
⎞
⎟
⎠
rr
I PP
--------- -
(
I
--------- -
⋅
UP,2
PP
12
D(ON)
⋅
1 d
2
. Since the inductor current has
f
f
2
.
S
S
–
2
⎞
⎟
⎠
. In Equation 27, the
⋅
d1
.
conduction loss.
)
t d1
+
, the switching frequency,
and t
I
------------------------------------ -
L PP
+
,
⎛
⎜
⎜
⎝
2
I
------
LOW,1
N
M
d2
12
UP,1
rr
⋅
–
1
, at the beginning
(
, it is conducted
I PP
--------- -
1 d
and the
2
–
.
⎞
⎟
⎟
⎠
and P
⋅
)
t d2
February 1, 2011
LOW,2
(EQ. 24)
(EQ. 25)
(EQ. 26)
(EQ. 27)
(EQ. 28)
(EQ. 29)
FN9290.5
rr
.
,