ADP3209CJCPZ-RL ON Semiconductor, ADP3209CJCPZ-RL Datasheet - Page 25

• Manufacturer Part Number: ADP3209CJCPZ-RL
• Description: IC CTLR BUCK 5BIT 1PH 32LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADP3209CJCPZ-RL

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 3.3 ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.4 ~ 1.25 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

C
The required output decoupling for processors and platforms is
typically recommended by Intel. For systems containing both
bulk and ceramic capacitors, however, the following guidelines
can be a helpful supplement.
Select the number of ceramics and determine the total ceramic
capacitance (C
capacitors used. Keep in mind that the best location to place
ceramic capacitors is inside the socket; however, the physical
limit is twenty 0805-size pieces inside the socket. Additional
ceramic capacitors can be placed along the outer edge of the
socket. A combined ceramic capacitor value of 40 µF to 50 µF
is recommended and is usually composed of multiple 10 µF or
22 µF capacitors.
Ensure that the total amount of bulk capacitance (C
its limits. The upper limit is dependent on the VID on-the-fly
output voltage stepping (voltage step, V
of V
for load release at a given maximum load step, ∆I
version of the IMVP-6+ specification allows a maximum V
overshoot (V
step-off load current.
where
To meet the conditions of these expressions and the transient
response, the ESR of the bulk capacitor bank (R
than two times the droop resistance, R
than C
specifications and may require less inductance. In addition, the
switching frequency may have to be increased to maintain the
output ripple.
OUT
(
(
ERR
SELECTION
); the lower limit is based on meeting the critical capacitance
X(MAX)
)
)
≥
= ln
≤
§
¨
¨
¨
¨
¨
©
−
, the system does not meet the VID on-the-fly
§
¨
¨
©
2
OSMAX
×
Z
§
¨
¨
©
). This is based on the number and type of
+
2
) of 10 mV more than the VID voltage for a
×
∆
×
·
¸
¸
¹
∆
×
·
¸
¸
¹
×
§
¨
¨
¨
©
1
+
§
¨
¨
©
−
O
V
. If the C
, in time, t
·
¸
¸
¸
¸
¸
¹
×
X
×
X(MIN)
) should be less
O
. The current
V
X
, with error
Rev. 2 | Page 25 of 32 | www.onsemi.com
) is within
·
¸
¸
¹
is greater
2
−
1
CCGFX
·
¸
¸
¸
¹
(12)
(13)
−
For example, if two pieces of 22 µF, 0805-size MLC capacitors
(C
change is 220 mV in 22 µs with a setting error of 10 mV. If k = 3.1,
solving for the bulk capacitance yields
= 992 µF
Using two 220 µF Panasonic SP capacitors with a typical ESR of
7 mΩ each yields C
Ensure that the ESL of the bulk capacitors (L
limit the high frequency ringing during a load change. This is
tested using
where:
system.
enough to avoid ringing during a load change. If the L
chosen bulk capacitor bank is too large, the number of ceramic
capacitors may need to be increased to prevent excessive
ringing.
For this multimode control technique, an all ceramic capacitor
design can be used if the conditions of Equations 12, 13, and 14
are satisfied.
§
¨
¨
¨
©
is limited to the square root of 2 to ensure a critically damped
Z
is about 450 pH for the two SP capacitors, which is low
1
(
(
= 44 µF) are used during a VID voltage change, the V
+
§
¨
¨
©
)
)
2 2
≥
≤
≤
≤
μs
§
¨
¨
¨
¨
¨
¨
©
44
3
§
¨
¨
©
1 .
×
22
μF
5
×
1.
2
1 .
560
0
×
×
174
mΩ
mV
5 (
(
5
X
2
560
nH
1 .
1 .
×
= 440 µF and R
V
+
×
mΩ
mΩ
10
×
×
56
nH
2
8
3
220
mV
)
1 .
0
)
A
2
2
×
nH
×
×
×
mV
8
5
2
. 1
·
¸
¸
¹
1 .
A
×
=
174
. 1
m
2
3 .
174
Ω
X
V
nH
·
¸
¸
¹
= 3.5 mΩ.
×
2
V
−
−
1
·
¸
¸
¸
¹
44
X
−
) is low enough to
μF
44
·
¸
¸
¸
¸
¸
¸
¹
μF
=
256
X
of the
CCGFX
µ
F
(14)