ADP3209CJCPZ-RL ON Semiconductor, ADP3209CJCPZ-RL Datasheet - Page 26

• Manufacturer Part Number: ADP3209CJCPZ-RL
• Description: IC CTLR BUCK 5BIT 1PH 32LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADP3209CJCPZ-RL

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 3.3 ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.4 ~ 1.25 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER MOSFETS
For typical 15 A per phase applications, the N-channel power
MOSFETs are selected for one high-side switch and one low-
side switch. The main selection parameters for the power
MOSFETs are V
voltage of the gate driver is 5 V, logic-level threshold MOSFETs
must be used.
The maximum output current, I
requirement for the low-side (synchronous) MOSFETs. With
conduction losses being dominant, the following expression
shows the total power that is dissipated in each synchronous
MOSFET in terms of the ripple current per phase (I
average total output current (I
where:
divided by the input voltage.
approximately
Knowing the maximum output current and the maximum
allowed power dissipation, the user can calculate the required
R
compatible MOSFET, the junction-to-ambient (PCB) thermal
impedance is 50°C/W. In the worst case, the PCB temperature is
70°C to 80°C during heavy load operation of the notebook, and a
safe limit for P
ature. Therefore, for this example (15 A maximum), the R
per MOSFET is less than 18.8 mΩ for the low-side MOSFET.
This R
therefore, the R
at room temperature, or 18.8 mΩ at high temperature.
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input must be small (less than 10% is recommended)
to prevent accidentally turning on the synchronous MOSFETs
when the switch node goes high.
The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction losses and
switching losses. Switching loss is related to the time for the
main MOSFET to turn on and off and to the current and
DS(ON)
is the duty cycle and is approximately the output voltage
is the inductor peak-to-peak ripple current and is
=
1 (
DS(SF)
for the MOSFET. For an 8-lead SOIC or 8-lead SOIC-
−
=
×
1 (
is also at a junction temperature of about 120°C;
)
×
−
SF
DS(SF)
is about 0.8 W to 1.0 W at 120°C junction temper-
GS(TH)
)
×
ª
«
«
¬
per MOSFET should be less than 13.3 mΩ
§
¨
¨
©
, Q
G
, C
·
¸
¸
¹
2
ISS
+
, C
O
12
1
):
O
RSS
, determines the R
×
, and R
§
¨
¨
©
·
¸
¸
¹
2
DS(ON)
º
»
»
¼
×
. Because the
(
)
DS(ON)
R
Rev. 2 | Page 26 of 32 | www.onsemi.com
) and the
DS(SF)
(15)
voltage that are being switched. Basing the switching speed on
the rise and fall times of the gate driver impedance and
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET:
where:
The most effective way to reduce switching loss is to use lower
gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following equation:
where
Typically, a user wants the highest speed (low C
main MOSFET, but such a device usually has higher on resistance.
Therefore, the user must select a device that meets the total power
dissipation (about 0.8 W to 1.0 W for an 8-lead SOIC) when
combining the switching and conduction losses.
For example, an IRF7821 device can be selected as the main
MOSFET (one in total; that is, n
C
T
synchronous MOSFET (two in total; that is, n
R
power dissipation per MOSFET at I
yields 178 mW for each synchronous MOSFET and 446 mW
for each main MOSFET. A third synchronous MOSFET is an
option to further increase the conversion efficiency and reduce
thermal stress.
Finally, consider the power dissipation in the driver. This is best
described in terms of the Q
the following equation:
where
The previous equation also shows the standby dissipation (I
times the VCC) of the driver.
J
DS(SF)
ISS
= 120°C), and an IR7832 device can be selected as the
is the total gate resistance.
is the total number of main MOSFETs.
is the input capacitance of the main MOSFET.
= 1010 pF (maximum) and R
is the total gate charge for each synchronous MOSFET.
=
= 6.7 mΩ (maximum at T
(
(
ª
«
¬
2
)
)
×
= 2
is the total gate charge for each main MOSFET, and
=
is the on resistance of the MOSFET.
×
×
(
×
ª
«
«
¬
§
¨
¨
©
×
×
·
¸
¸
¹
2
G
+
×
+
for the MOSFETs and is given by
12
1
MF
J
×
×
= 120°C). Solving for the
DS(MF)
×
§
¨
¨
©
= 1), with approximately
O
= 15 A and I
×
= 18 mΩ (maximum at
·
¸
¸
¹
)
2
+
º
»
»
¼
×
×
SF
º
»
¼
ISS
= 2), with
×
(
) device for a
R
= 5.0 A
)
CC
(16)
(17)
(18)