ADP3208CJCPZ-RL ON Semiconductor, ADP3208CJCPZ-RL Datasheet - Page 18

• Manufacturer Part Number: ADP3208CJCPZ-RL
• Description: IC CTLR BUCK 7BIT IMVP6 48LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADP3208CJCPZ-RL

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 3.3 ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Output Voltage: 10 mV
• Output Current: 40 A
• Input Voltage: 19 V
• Supply Current: 6 mA
• Switching Frequency: 300 KHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 10 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Current Sensing
Amplifier (CSA) to monitor the total output current of the
converter for proper voltage positioning vs. load current and
for over current detection. Sensing the current delivered to
the load is an inherently more accurate method than
detecting peak current or sampling the current across a sense
element, such as the low−side MOSFET. The CSA can be
configured several ways, depending on system optimization
objectives, and the current information can be obtained by:
•
•
•
connected to the output voltage. At the negative input (that
is, the CSSUM pin of the CSA), signals from the sensing
element (in the case of inductor DCR sensing, signals from
the switch node side of the output inductors) are summed
together by series summing resistors. The feedback resistor
between the CSCOMP and CSSUM pins sets the gain of the
CSA, and a filter capacitor is placed in parallel with this
resistor. The current information is then given as the voltage
difference between the CSCOMP and CSREF pins. This
signal is used internally as a differential input for the current
limit comparator.
CSCOMP and CSREF pins with the midpoint connected to
the LLINE pin can be used to set the load line required by the
microprocessor specification. The current information to set
the load line is then given as the voltage difference between
the LLINE and CSREF pins. This configuration allows the
load line slope to be set independent from the current limit
threshold. If the current limit threshold and load line do not
have to be set independently, the resistor divider between the
CSCOMP and CSREF pins can be omitted and the
CSCOMP pin can be connected directly to LLINE. To
disable voltage positioning entirely (that is, to set no load
line), LLINE should be tied to CSREF.
has a low offset input voltage and the sensing gain is set by
an external resistor ratio.
Active Impedance Control Mode
of the output current, the signal that is proportional to the
total output current, converted from the voltage difference
between LLINE and CSREF, can be scaled to be equal to the
required droop voltage. This droop voltage is calculated by
multiplying the droop impedance of the regulator by the
output current. This value is used as the control voltage of
the PWM regulator. The droop voltage is subtracted from the
DAC reference output voltage, and the resulting voltage is
The ADP3208C includes a dedicated Current Sense
At the positive input of the CSA, the CSREF pin is
An additional resistor divider connected between the
To provide the best accuracy for current sensing, the CSA
To control the dynamic output voltage droop as a function
Output inductor ESR sensing without the use of a
thermistor for the lowest cost
Output inductor ESR sensing with the use of a
thermistor that tracks inductor temperature to improve
accuracy
Discrete resistor sensing for the highest accuracy
http://onsemi.com
18
used as the voltage positioning setpoint. The arrangement
results in an enhanced feed−forward response.
Current Control Mode and Thermal Balance
current of each phase. The phase current information is
combined
current−balancing feedback system that is optimized for
initial current accuracy and dynamic thermal balance. The
current balance information is independent from the total
inductor current information used for voltage positioning
described in the Active Impedance Control Mode section.
transient response of the system is optimal. The ADP3208C
monitors the supply voltage to achieve feed forward control
whenever the supply voltage changes. A resistor connected
from the power input voltage rail to the RAMP pin
determines the slope of the internal PWM ramp. More detail
about programming the ramp is provided in the Application
Information section.
balance circuitry if a good layout is used. However, if
mismatch is desired due to uneven cooling in phase, external
resistors can be added to individually control phase currents
as long as the phase currents are mismatched by less than
30%. If unwanted mismatch exceeds 30%, a new layout that
improves phase symmetry should be considered.
control the duty cycle of the separate phases. Figure 28
shows the addition of two resistors from each switch node
to the RAMP pin; this modifies the ramp−charging current
individually for each phase. During Phase 1, SW Node 1 is
high (practically at the input voltage potential) and SW
Node 2 is low (practically at the ground potential). As a
consequence, the RAMP pin, through the R2 resistor, sees
the tap point of a divider connected to the input voltage,
where R
element of the divider. During Phase 2, the voltages on SW
Node 1 and SW Node 2 switch and the resistors swap
functions. Tuning R
optimally set for each phase. To increase the current for a
given phase, decrease R
Voltage Control Mode
voltage mode control loop. The noninverting input voltage
The ADP3208C has individual inputs for monitoring the
The magnitude of the internal ramp can be set so that the
The ADP3208C should not require external thermal
In 2−phase operation, alternate cycles of the internal ramp
A high−gain bandwidth error amplifier is used for the
VDC
Figure 28. Optional Current Balance Resistors
C
SW1
RAMP
with
is the upper element and R
R1
20
an
SW1
R2
SW
Reserved for Thermal Balance Tune
and R
internal
R
ADP3208C
for that phase.
R
SW2
SW1
SW2
allows the current to be
ramp
SWITCH NODE 1
SWITCH NODE 2
SW2
to
is the lower
create
a