ADP3208C ON Semiconductor, ADP3208C Datasheet

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ADP3208C

Manufacturer Part Number
ADP3208C
Description
7-bit,programmable,dual- Phase,mobile,cpu,synchronous Buck Controller
Manufacturer
ON Semiconductor
Datasheet

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ADP3208CJCPZ-RL
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FEATURES
Single-chip solution
Integrated MOSFET drivers
Input Voltage Range of 3.3 V to 22 V
Selectable 1- or 2-phase operation with up to 1 MHz per
Guaranteed ±8 mV worst-case differentially sensed core
Automatic power-saving mode maximizes efficiency with
Soft transient control reduces inrush current and audio noise
Active current balancing between output phases
Independent current limit and load line setting inputs for
Built-in power-good blanking supports
7-bit, digitally programmable DAC with 0.3 V to 1.5 V output
Short-circuit protection with latch-off delay
Clock enable output delays the CPU clock until the core
Output load current monitor
48-lead LFCSP
APPLICATIONS
Notebook power supplies for next-generation Intel processors
May 2008– Rev. 1
Fully compatible with the Intel® IMVP-6+™ specifications
phase switching frequency
voltage error over temperature
light load during deeper sleep operation
additional design flexibility
voltage identification (VID) on-the-fly transients
voltage is stable
Preliminary
Phase,Mobile,CPU,Synchronous
7-Bit,Programmable,Dual-
GENERAL DESCRIPTION
The ADP3208C is a highly efficient, multiphase, synchronous
buck switching regulator controller. With its integrated drivers,
the ADP3208C is optimized for converting the notebook
battery voltage into the core supply voltage required by high
performance Intel processors. An internal 7-bit DAC is used to
read a VID code directly from the processor and to set the CPU
core voltage to a value within the range of 0.3 V to 1.5 V. The
phase relationship of the output signals ensures interleaved 2-
phase operation.
The ADP3208C uses a multimode architecture run at a
programmable switching frequency and optimized for efficiency
depending on the output current requirement. The ADP3208C
switches between single- and dual-phase operation to maximize
efficiency with all load conditions. The chip includes a
programmable load line slope function to adjust the output voltage
as a function of the load current so that the core voltage is always
optimally positioned for a load transient. The ADP3208C also
provides accurate and reliable short-circuit protection,
adjustable current limiting, and a delayed power-good output.
The IC supports on-the-fly output voltage changes requested by
the CPU.
The ADP3208C is specified over the extended commercial
temperature range of -10°C to 100°C and is available in a 48-lead
LFCSP.
Buck Controller
ADP3208C

Related parts for ADP3208C

ADP3208C Summary of contents

Page 1

... The chip includes a programmable load line slope function to adjust the output voltage as a function of the load current so that the core voltage is always optimally positioned for a load transient. The ADP3208C also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power-good output. ...

Page 2

... ADP3208C COMP LLINE PSI PSI TTSNS VRTT PWRGD CLKEN FBRTN FUNCTIONAL BLOCK DIAGRAM GND VCC EN RPM RT RAMP VARFREQ UVLO UVLO Oscillator Shutdown Shutdown and Bias and Bias Driver VEA Current Current Balancing Balancing + Σ Σ Circuit Circuit REF + CSREF OVP Σ Σ ...

Page 3

... COMP Pin Ramp ........................................................................35 Current Limit Setpoint...............................................................36 Output Current monitor ............................................................36 Feedback Loop Compensation Design ....................................36 C Selection and Input Current di/dt Reduction ..................37 IN Selecting Thermal Monitor Components................................38 Tuning Procedure for ADP3208C ............................................38 Layout and Component Placement ..........................................39 Outline Dimension .........................................................................41 Ordering Guide ...........................................................................41 Rev Page www.onsemi.com ADP3208C ...

Page 4

... ADP3208C SPECIFICATIONS VCC = PVCC1 = PVCC2 = BST1 = BST2 = high = 5 V, FBRTN = GND = SW1 = SW2 = PGND1 = PGND2 = low = VARFREQ = high, DPRSLP = 0 V, PSI = 1. VID device) has a positive sign kΩ. REF Table 1. Parameter Symbol VOLTAGE CONTROL VOLTAGE ERROR AMPLIFIER (VEAMP) 2 FB, LLINE Voltage Range ...

Page 5

... PSI = L 1-ph configuration Measured from OCP event to PWRGD de-assertion Measured from ILIMP to IMON LIM = −20 μA I LIM = −10 μA I LIM = −5 μA I LIM Relative to FBRTN, ILIMP = -30 uA Rev Page www.onsemi.com ADP3208C Min Typ Max 1.57 1.7 1.78 −350 −300 −70 −5 50 150 0 200 ...

Page 6

... ADP3208C Parameter Symbol PULSE WIDTH MODULATOR CLOCK OSCILLATOR RT Voltage V RT PWM Clock Frequency f CLK 2 Range PWM Clock Frequency f CLK RAMP GENERATOR RAMP Voltage V RAMP 2 RAMP Current Range I RAMP PWM COMPARATOR 2 PWM Comparator Offset V OSRPM RPM COMPARATOR RPM Current I RPM 2 RPM Comparator Offset ...

Page 7

... VCC is rising VCC is falling BST = PVCC BST = PVCC BST = PVCC nF, Figure 2 L BST = PVCC nF, Figure 2 L BST = PVCC, Figure 2 DRVH (Shutdown switching Rev Page www.onsemi.com ADP3208C Min Typ Max Units 0.3 V 0.7 V μ μA ...

Page 8

... ADP3208C Parameter Symbol Transition Times tr DRVL tf DRVL Propagation Delay Times tpdh SW Transition Timeout t TOSW SW Off Threshold V OFFSW PVCC Quiescent Current BOOTSTRAP RECTIFIER SWITCH On Resistance 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 Guaranteed by design or bench characterization, not production tested. ...

Page 9

... TIMING DIAGRAM Timing is referenced to the 90% and 10% points, unless otherwise noted. IN tpdl DRVL DRVL DRVH (WITH RESPECT TO SW DRVL tpdh tr DRVH DRVH V TH Figure 2. Timing Diagram Rev Page www.onsemi.com ADP3208C tpdl tr DRVH DRVL tf DRVH V TH tpdh DRVL 1V ...

Page 10

... ADP3208C ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC, PVCC1, PVCC2 FBRTN, PGND1, PGND2 BST1, BST2 DC t < 200 ns BST1 to SW1, BST2 to SW2 SW1, SW2 DC t < 200 ns DRVH1 to SW1, DRVH2 to SW2, DRVL1 to PGND1, DRVL2 to PGND2 DC t < 200 ns RAMP (in Shutdown) DC All Other Inputs and Outputs ...

Page 11

... RPM Mode Timing Control Input. A resistor between this pin or IRPM pin to ground sets the RPM mode turn-on threshold voltage resistor is connected between this pin to ground, IRPM pin must remain floating. This pin sets the internal bias currents. A 80kOhm resistor is connected from this pin to ground. Rev Page www.onsemi.com ADP3208C BST1 DRVH1 SW1 PVCC1 ...

Page 12

... ADP3208C Pin No. Mnemonic 16 LLINE 17 CSCOMP 18 CSREF 19 CSSUM 20 RAMP 21 ILIMN 22 ILIMP GND 25 BST2 26 DRVH2 27 SW2 28 PVCC2 29 DRVL2 30 PGND2 31 PGND1 32 DRVL1 33 PVCC1 34 SW1 35 DRVH1 36 BST1 37 VCC VID6 to VID0 46 PSI 47 DPRSTP 48 DPRSLP Description Load Line Programming Input. The center point of a resistor divider connected between CSREF and CSCOMP can be tied to this pin to set the load line slope ...

Page 13

... TEST CIRCUITS Figure 4. Closed-Loop Output Voltage Accuracy Figure 5. Current Sense Amplifier, V 10kΩ ΔV 1.0V OS Rev Page www.onsemi.com ADP3208C ADP3208C 5V VCC 37 COMP LLINE 16 CSREF VID DAC 18 GND Δ ΔV ΔV=0mV FB ΔV Figure 6. Positioning Accuracy ...

Page 14

... Rev Page www.onsemi.com ADP3208C ...

Page 15

... V = 1.2 V OUT f = 305 kHz SW2 SW1 Rev Page www.onsemi.com ADP3208C SW2 SW1 OUTPUT VOLTAGE Input = 12V, Output = 44A Load Step Figure 9. . Load Transient with 2 Phases OUTPUT RIPPLE CSREF to CSCOMP SW1 SW2 Input = 12V, Output = 1.1V No Load Figure 10. Switching Waveforms in 2 Phase ...

Page 16

... ADP3208C 400 350 VARFREQ = 0V 300 250 VARFREQ = 5V 200 150 100 50 0 0.25 0.5 0.75 1 VID OUTPUT VOLTAGE (V) Figure 12. Switching Frequency vs. VID Output Voltage in PWM Mode 350 300 250 200 150 100 0.5 OUTPUT VOLTAGE (V) Figure 13. Switching Frequency vs. Output Voltage in RPM Mode 1200 1000 800 ...

Page 17

... Figure 20. PSI Transition SWITCH NODE 1 OUTPUT VOLTAGE SWITCH NODE 1 SWITCH NODE 2 8.00A OUTPUT VOLTAGE DPRSLP PSI Rev Page www.onsemi.com ADP3208C SWITCH NODE 2 Figure 21. PSI Transition OUTPUT VOLTAGE DPRSLP PSI = HI GH LOA Figure 26. DPRSLP Transition SWITCH NODE 1 SWITCH NODE 2 PSI = HIG Figure 27 ...

Page 18

... ADP3208C OUTPUT VOLTAGE DPRSLP SWITCH NODE 2 Figure28. DPRSLP Transition OUTPUT VOLTAGE DPRSLP SWITCH NODE 2 Figure29. DPRSLP Transition SWITCH NODE 1 PSI = LOW LOA SWITCH NODE 1 PSI = LOW LOA Rev Page www.onsemi.com ...

Page 19

... set low (user-selected dual-phase mode) during a VID transient or with a heavy load condition (indicated by DPRSLP being low and PSI being high), the ADP3208C runs in 2-phase, interleaved PWM mode to achieve minimal V ripple and the best transient performance possible. If the load becomes light (indicated by PSI being low or DPRSLP being high), ADP3208C switches to single-phase mode to maximize the power conversion efficiency ...

Page 20

... ADP3208C Table 4. Phase Number and Operation Modes PSI No. DPRSLP VID Transition * * Yes don’t care. 2 VID transient period is the time following any VID change, including entry into and exit from deeper sleep mode. The duration of VID transient period is the same as that of PWRGD masking time ...

Page 21

... RD 5V BST2 GATE DRIVER BST DRVH FLIP-FLOP DRVH2 SW2 DRVL DRVL2 RD VDC CSREF + – – CSSUM FBRTN LLINE CSCOMP Rev Page www.onsemi.com ADP3208C VCC LOAD VCC ...

Page 22

... ADP3208C Setting Switch Frequency Master Clock Frequency in PWM Mode When the ADP3208C runs in PWM, the clock frequency is set by an external resistor connected from the RT pin to GND. The frequency is constant at a given VID code but varies with the VID voltage: the lower the VID voltage, the lower the clock frequency ...

Page 23

... The power-up sequence, including the soft start is illustrated in Figure 25. After EN is asserted high, the soft start sequence starts. The core voltage ramps up linearly to the boot voltage. The ADP3208C regulates at the boot voltage for 100 μs. After the is the SW2 boot time is completed, CLKEN# is asserted low. After CLKEN# is asserted low for 9ms, PWRGD is asserted high ...

Page 24

... Next, when initial reset is over, the chip detects the number of phases set by the user, and gives a go signal to start soft start. The ADP3208C reads the VID codes provided by the CPU on VID0 to VID6 input pins after CLKEN# is asserted low.The PWRGD signal is asserted after a t delay of about 9 ms, as specified by IMVP-6+ ...

Page 25

... FETs are off and no current flows into the inductor (see Figure 31). Figure 32 shows the inductor current and switch node voltage in DCM. In DCM with a light load, the ADP3208C monitors the switch node voltage to determine when to turn off the low-side FET. Figure 33 shows a typical waveform in DCM with load current ...

Page 26

... When the OVP feature is triggered, the ADP3208C is latched off. The latch-off function can be reset by removing and reapplying VCC to the ADP3208C or by briefly pulling the EN pin low. Rev Page www.onsemi.com 4 OUTPUT VOLTAGE 20mV/DIV SWITCH NODE 5V/DIV 2 ...

Page 27

... PGDELAY pins to ground, and drives the DRVH and DRVL outputs low. The user must adhere to proper power-supply sequencing during startup and shutdown of the ADP3208C. All input pins must be at ground prior to removing or applying VCC, and all output pins should be left in high impedance state while VCC is off. ...

Page 28

... ADP3208C added in parallel with R to filter the inductor ripple. The MON IMON pin is clamped to prevent it from going above 1.15V Rev Page www.onsemi.com ...

Page 29

... 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 V 1 Rev Page www.onsemi.com ADP3208C VID5 VID4 VID3 VID2 VID1 VID0 ...

Page 30

... Figure 35. Typical Dual-Phase Application Circuit Rev Page www.onsemi.com ADP3208C ...

Page 31

... For good initial accuracy and frequency stability recommended to use a 1% resistor. SETTING THE SWITCHING FREQUENCY FOR RPM OPERATION OF PHASE 1.4375 V During the RPM mode operation of Phase 1, the ADP3208C runs in pseudo constant frequency, given that the load current is high enough for continuous current mode. While 1.3535 V OFL discontinuous current mode, the switching frequency is reduced with the load current in a linear manner ...

Page 32

... ADP3208C current. Equation 4 can be used to determine the minimum inductance based on a given output ripple voltage. × − VID MIN I × × × − × ≥ VID O MIN L × RIPPLE Solving Equation 4 for peak-to-peak output ripple ...

Page 33

... IMVP-6+ specification allows a maximum V overshoot (V step-off load current MIN MAX (8) where Rev Page www.onsemi.com ADP3208C Calculate values for R and R by using the following CS1 CS2 equations: = × × CS1 CS ...

Page 34

... MOSFETs must be used. The maximum output current, I requirement for the low-side (synchronous) MOSFETs. In the ADP3208C, currents are balanced between phases; the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (n dominant, the following expression shows the total power that ...

Page 35

... CC ⎦ This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input: V where C resistance of the regulator. For this example, the overall ramp signal is 1.85 V. Rev Page www.onsemi.com ADP3208C × × × × ...

Page 36

... R A Type III compensator on the voltage feedback is adequate for proper compensation of the output filter. Figure 37 shows the Type III amplifier used in the ADP3208C. Figure 38 shows the locations of the two poles and two zeros created by this amplifier. (27) MON Rev Page www.onsemi.com ...

Page 37

... The expressions that follow compute the time constants for the poles and zeros in the system and are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Tuning Procedure for ADP3208C section): × × ...

Page 38

... Build a circuit based on the compensation values computed from the design spreadsheet. 2. Connect a dc load to the circuit. at 100°C). TH1 3. Turn on the ADP3208C and verify that it operates properly. 4. Check for jitter with no load and full load conditions. Set the DC Load Line 1. Measure the output voltage with no load (V that this voltage is within the specified tolerance range ...

Page 39

... ACDRP LAYOUT AND COMPONENT PLACEMENT The following guidelines are recommended for optimal performance of a switching regulator system. Rev Page www.onsemi.com ADP3208C V DROOP V TRAN1 V TRAN2 Figure 42. Transient Setting Waveform, Load Step ...

Page 40

... V inductors of all the phases the back of the ADP3208C package, there is a metal pad that can be used to heat sink the device. Therefore, running vias under the ADP3208C is not recommended because the metal pad may cause shorting between vias. ...

Page 41

... Rev Page www.onsemi.com ADP3208C 0.30 0.23 0.60 MAX 0.18 PIN 1 INDICATOR 48 1 EXPOSED 5.25 PAD 5.10 SQ (BOTTOM VIEW) 4. 0.25 MIN 5.50 REF Package Package Marking Option CP-48-1 Line 1: ADP3208C Line 2: AWLYYWG ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative Ordering Quantity 2,500 ...

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