ADP3156JR-2.5 Analog Devices Inc, ADP3156JR-2.5 Datasheet - Page 9

• Manufacturer Part Number: ADP3156JR-2.5
• Description: IC REG BUCK DUAL SW 2.5V 16-SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADP3156JR-2.5

• Rohs Status: RoHS non-compliant
• Applications: Controller, Intel Pentium® III
• Voltage - Input: 3V, 5V
• Number Of Outputs: 2
• Voltage - Output: 2.5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)

current of 1.7 A and an average short-circuit current of about
6.5 A—meaning that there is actually a small degree of short-
circuit current foldback. To safely carry the maximum current,
the sense resistor must have a power rating of at least (11.2 A –
1.07 A)
Current Transformer Option
An alternative to using a low value and high power current sense
resistor is to reduce the sensed current by using a low cost cur-
rent transformer and a diode. The current can then be sensed
with a small size, low cost SMT resistor. Using a transformer
with one primary and 50 secondary turns reduces the worst-case
resistor dissipation to a few mW. Another advantage of using
this option is the separation of the current and voltage sensing,
which makes the voltage sensing more accurate.
Power MOSFETs
Two external N-channel power MOSFETs must be selected for
use with the ADP3156, one for the main switch, and an identi-
cal one for the synchronous switch. The main selection param-
eters for the power MOSFETs are the threshold voltage V
and the on resistance R
dictates whether standard threshold or logic-level threshold
MOSFETs must be used. For V
MOSFETs (V
drop below 8 V, logic-level threshold MOSFETs (V
2.5 V) are strongly recommended. Only logic-level MOSFETs
with V
should be used.
The maximum output current I
requirement for the two power MOSFETs. When the ADP3156
is operating in continuous mode, the simplifying assumption can
be made that one of the two MOSFETs is always conducting
the average load current. For V
maximum duty ratio of the high side FET is:
The duty ratio of the low side (synchronous rectifier) FET un-
der the maximum load condition is:
The maximum rms current of the high side FET is:
The maximum rms current of the low side FET is:
= 7.03 A rms
The R
dissipation. Allowing 8% of the maximum output power for
FET dissipation, the total dissipation will be:
Allocating half of the total dissipation for the high side FET and
half for the low side FET, the required minimum FET resis-
tances will be:
Note that there is a trade-off between converter efficiency and
cost. Larger FETs reduce the conduction losses and allow
higher efficiency, but increase the system cost. If efficiency is
not a major concern, the International Rectifier IRL3103 is an
REV. 0
I
I
= 7.32 A rms
RMSHS
RMSLS
R
R
D
DS(ON)HSF(MIN)
DS(ON)LSF(MIN)
MAXHF
DS(ON)
GS
2
= [D
= [D
ratings higher than the absolute maximum of V
12.9 mW = 1.3 W.
= (1 – f
MAXLF
MAXHF
for each FET can be derived from the allowable
GS(TH)
P
FETALL
D
= 1 W
= 1 W
MIN
(I
MAXLF
(I
LVALLEY
< 4 V) may be used. If V
LVALLEY
DS(ON)
= 0.08 V
t
OFF
= 1 – D
48%/(7.03A)
52%/(7.32A)
2 + I
) = (1 – 150 kHz
2 + I
. The minimum input voltage
IN
OMAX
IN
LPEAK
O
MAXHF
LPEAK
= 5 V and V
I
> 8 V, standard threshold
OMAX
determines the R
2 + I
2 + I
2
= 48%
2
= 1.0 W
= 9.7 m
= 9.7 m
LVALLEY
LVALLEY
IN
OUT
3.2 s) = 52%
is expected to
I
= 1.8 V, the
I
LPEAK
GS(TH)
LPEAK
DS(ON)
CC
)/3]
)/3]
GS(TH)
<
0.5
0.5
–9–
economical choice for both the high side and low side positions.
Those devices have an R
+25 C. The low side FET is turned on with at least 10 V. The
high side FET, however, is turned on with only 12 V – 5 V =
7 V. Checking the typical output characteristics of the device in
the data sheet, shows that for an output current of 10 A, and at
a V
slightly above the one specified at a V
tance increase due to the reduced gate drive can be neglected.
The specified R
temperature of +140 C must be modified by an R
plier, using the graph in the data sheet. In this case:
Using this multiplier, the expected R
1.7
The high side FET dissipation is:
P
where the second term represents the turn-off loss of the FET.
(In the second term, Q
the gate for turn-off and I
sheet, Q
provided by the ADP3156 is about 1 A.)
The low side FET dissipation is:
(Note that there are no switching losses in the low side FET.)
To maintain an acceptable MOSFET junction temperature,
proper heat sinking should be used. The heat sink and airflow
are chosen based on how low the impedance must be reduced in
order to keep the MOSFET’s junction temperature at an ac-
ceptably low level, according to the formula:
where
ent air (and depends on airflow), T
mined maximum acceptable operating temperature of the
MOSFET, and the last two factors are the thermal resistance
from junction-to-case of the device, and case-to-heat sink. Typi-
cally, the junction-to-case thermal resistance is 2 C/W, and the
case-to-heat sink resistance is 0.5 C/W.
C
In continuous-inductor-current mode, the source current of the
high side MOSFET is a square wave with a duty ratio of V
To keep the input ripple voltage at a low value, one or more
capacitors with low equivalent series resistance (ESR) and ad-
equate ripple-current rating must be connected across the input
terminals. The maximum rms current of the input bypass ca-
pacitors is:
For an FA-type capacitor with 2700 mF capacitance and 10 V
voltage rating, the ESR is 34 m and the allowed ripple current
at 100 kHz (and similar frequencies) is 1.94 A. At +105 C, two
such capacitors may be connected in parallel to handle the cal-
culated ripple current.
To further reduce the effect of the ripple voltage on the system
supply voltage bus and to reduce the input-current di/dt to
below the recommended maximum of 0.1 A/ s, an additional
small inductor should be inserted between the converter and the
supply bus (see Figure 2).
DFETHS
IN
GS
Selection and Input Current di/dt Reduction
of 7 V, the V
14 = 24 m .
HA
G
= I
I
CINRMS
is about 50 nC–70 nC and the gate drive current
is the thermal resistance from the heat sink to ambi-
RMSHS
HA
DS(ON)
P
= [(T
= I
2
DFETLS
R
DS
DS(ON)
OMAX
JMAXOP
is 0.15 V. This gives an R
at the expected highest FET junction
G
R
= I
DS(ON)
DS(ON)MULT
is the gate charge to be removed from
G
[D
+ 0.5 V
rmsls
is the gate current. From the data
MAX
– T
2
of 14 m at V
R
A
DS(ON)
)¸P
IN
(1–D
JMAXOP
I
= 1.7
DFET
DS(ON)
LPEAK
GS
= 0.49 W
MAX
of 10 V, so the resis-
] –
Q
is the user-deter-
at +140 C is
)]
G
JC
0.5
f
GS
ADP3156
MIN
–
DS(ON)
= 3.5 A
= 10 V and at
/I
DS(ON)
CH
G
~ 2.54 W
only
multi-
O
/V
lN
.