EL7585AILZ-T13 Intersil, EL7585AILZ-T13 Datasheet - Page 17

• Manufacturer Part Number: EL7585AILZ-T13
• Description: IC POWER SUPPLY TFT-LCD 20-QFN
• Manufacturer: Intersil

Specifications of EL7585AILZ-T13

• Applications: Converter, TFT, LCD
• Voltage - Input: 3 ~ 5 V
• Number Of Outputs: 4
• Voltage - Output: 5.5 ~ 20 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of 140°C, the device will shut
down.
Layout Recommendation
The device's performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
Demo Board Layout
1. Place the external power components (the input
2. Place V
3. Minimize the length of traces carrying fast signals and
4. All feedback networks should sense the output voltage
5. The power ground (PGND) and signal ground (SGND)
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
high current.
directly from the point of load, and be as far away from LX
node as possible.
pins should be connected at only one point near the main
decoupling capacitors.
REF
and V
FIGURE 27. TOP LAYER
DD
bypass capacitors close to the pins.
17
EL7585A
A two-layer demo board is available to illustrate the proper
layout implementation. A four-layer demo board can be used
to further optimize the layout recommendations.
6. The exposed die plate, on the underneath of the
7. To minimize the thermal resistance of the package when
8. A signal ground plane, separate from the power ground
9. Minimize feedback input track lengths to avoid switching
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return
connections for feedback resistor networks (R
R
C
noise pick-up.
41
7
and the integrator capacitor C
) and the V
FIGURE 28. BOTTOM LAYER
REF
capacitor, C
22
23
, the C
.
DELAY
1
March 9, 2006
capacitor
, R
FN7523.3
11
,