ISL6217CV Intersil, ISL6217CV Datasheet - Page 14

• Manufacturer Part Number: ISL6217CV
• Description: IC CTRLR PWM INTEL PENT 38-TSSOP
• Manufacturer: Intersil

Specifications of ISL6217CV

• Applications: Controller, Intel Pentium® IMVP-IV, IMVP+
• Voltage - Input: 5.5 ~ 25 V
• Number Of Outputs: 1
• Operating Temperature: -10°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Output: -

PGOOD
As previously described, the ISL6217 PGOOD pin operates
as both an input and an output. During start-up, the PGOOD
pin operates as an input (Refer to Figure 10).
FIGURE 10.
As per the IMVP-IV™ and IMVP-IV+™ specification, once
the ISL6217 CORE regulator regulates to the “Boot” voltage,
it waits for the PGOOD logic HIGH signals from the Vccp
and Vcc_mch regulators. The Intersil ISL6227 is a perfect
choice for these two supplies, as it is a dual regulator and
has independent PGOOD functions for each supply. Once
these two supplies are within regulation, PGOOD Vccp and
PGOOD Vcc_mch will be high impedance, and will allow the
PGOOD of the ISL6217 to sink approximately 2.6mA to
ground through the internal MOSFET, shown in Figure 10.
The ISL6217 detects this current and starts an internal
PGOOD timer.
The current sourced into the PGOOD pin is critical for proper
start-up operation. The pullup resistor, R pullup is sized to
give a minimum of 2.6mA of current sourced into the
PGOOD pin when the system is enabled and the Vccp and
Vcc_mch supplies are in regulation.
As given in the electrical specifications of this document, the
PGOOD MOSFET r DSON is given as 82Ω maximum. If 3.3V
is used as the supply, then the pullup resistor is given by the
following equation:
where Vsource is the supply minus 5% for tolerance. This
will insure that approximately 2.6mA will be sourced into the
PGOOD pin for worst case conditions of low supply and
largest MOSFET r DSON .
Once the proper level of PGOOD current is detected, the
ISL6217 then captures the VID and regulates to this value.
The PGOOD timer is a function of the internal clock and
switching frequency. The internal PGOOD delay can be
calculated as follows:
Timer Delay = 3072 / FSW
The ISL6217 controller regulates the CORE output voltage
to the VID command, and once the timer has expired, the
PGOOD output is allowed to go high.
NOTE: the PGOOD functions of the V CC_CORE , Vccp and
R
Pullup
EN
3ms-12ms
RST#
=
START
Vcc_mch regulators are wire OR’d together to create the
system signal “IMVP4_PWRGD”. If any of the supplies fall
outside the regulation window, their respective PGOOD pins
t
IPGT
Vsource
2
6 .
mA
UV# and OV#
CPU-UP# =
~ 100ns
INTERNAL PGOOD CIRCUITRY FOR THE ISL6217
CORE VOLTAGE REGULATOR
S
R
−
r
CLR
t
Q
Q
DSON
(
START
max
PGOOD
)
=
ISL6217
3
14
3 .
−
2
1.2K
6 .
. 0
mA
05
IMVP4_PWRGD
CLK_ENABLE#
( )
3.3V
3
3 .
10K
3.3V
−
82
10K
≈
3.3V
. 1
k 2
Ω
PGOOD
PGOOD
V cc_mch
(EQ. 4)
(EQ. 5)
ISL6227
V ccp
ISL6217
Overvoltage
The VSEN voltage is compared with an internal
overvoltage protection (OVP) reference, set to 112% of the
VID voltage. If the VSEN voltage exceeds the OVP
reference, a comparator simultaneously sets the OV latch,
and pulls the PWM signal low. The drivers turn on the lower
MOSFETs, shunting the converter output to ground. Once
the output voltage falls below 102% of the set point, the
high side and low side MOSFETs are held off. This
prevents dumping of the output capacitors back through the
output inductors and lower MOSFETs, which would cause
a negative voltage on the CORE output.
This architecture eliminates the need of a high current,
Schottky diode on the output. If the overvoltage condition
persists, the outputs are cycled between output low and
output “off”, similar to a hysteretic regulator. The OV latch is
reset by cycling the VDD supply voltage to initiate a POR.
Depending on the mode of operation, the overvoltage
setpoint is 112% of the VID, Deep or Deeper Sleep
setpoint.
Undervoltage
The VSEN pin is also compared to an undervoltage (UV)
reference which is set to 84% of the VID, Deep or Deeper
Sleep set point, depending on the mode of operation. If the
VSEN voltage is below the UV reference for more than 32
consecutive phase clock cycles, the power good monitor
triggers the PGOOD pin to go low, and latches the chip off
until power is reset to the chip, or the EN pin is toggled.
Overcurrent
The R ISEN resistor scales the voltage sampled across the
lower MOSFET and provides current feedback proportional
to the output current of each active channel (Refer to
Figure 9). The ISEN currents from all the active channels
are averaged together to form a scaled version of the total
output current, I AVERAGE . I AVERAGE is compared with
an internally generated overcurrent trip threshold, which is
proportional to the current sourced from the OCSET pin,
I OCSET . The overcurrent trip current source is
programmable and described in the “Overcurrent Setting -
OCSET” section of this document.
If I AVERAGE exceeds the I OCSET level, an up/down
counter in enabled. If I AVERAGE does not fall below
I OCSET within 32 phase cycle counts, the PGOOD pin
transitions low and latches the chip off. If normal operation
resumes within the 32 phase cycle count window, the
controller will continue to operate normally (Refer to the
“Block Diagram” ).
NOTE: due to “DROOP” there is inherent current limit, since load
are pulled low, which forces IMVP4_PWRGD low. PGOOD
of the ISL6217 is internally disabled during all VID and
Mode transitions.
current cannot exceed the amount that would command an
output voltage lower than 84% of the VID voltage. This
would result in an undervoltage shutdown, and would also
cause the PGOOD pin to transition low and latch the chip
off.