LTC1772ES6#TRMPBF Linear Technology, LTC1772ES6#TRMPBF Datasheet - Page 7
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LTC1772ES6#TRMPBF
Manufacturer Part Number
LTC1772ES6#TRMPBF
Description
IC DC/DC CNTRLR STEP-DWN SOT23-6
Manufacturer
Linear Technology
Type
Step-Down (Buck)r
Datasheet
1.LTC1772ES6TRMPBF.pdf
(12 pages)
Specifications of LTC1772ES6#TRMPBF
Internal Switch(s)
No
Synchronous Rectifier
No
Number Of Outputs
1
Voltage - Output
0.8 ~ 9.8 V
Current - Output
1A
Frequency - Switching
550kHz
Voltage - Input
2.5 ~ 9.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
TSOT-23-6, TSOT-6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-
Other names
LTC1772ES6#TRMPBFTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
APPLICATIONS
where f is the operating frequency. Accepting larger values
of I
higher output voltage ripple and greater core losses. A
reasonable starting point for setting ripple current is
I
occurs at the maximum input voltage.
In Burst Mode operation on the LTC1772, the ripple
current is normally set such that the inductor current is
continuous during the burst periods. Therefore, the peak-
to-peak ripple current must not exceed:
This implies a minimum inductance of:
A smaller value than L
however, the inductor current will not be continuous
during burst periods.
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af-
ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will in-
crease. Ferrite designs have very low core losses and are
preferred at high switching frequencies, so design goals
can concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
RIPPLE
(Use V
I
L
RIPPLE
RIPPLE
MIN
= 0.4(I
=
IN(MAX)
allows the use of low inductances, but results in
≤
®
f
V
⎛
⎜
⎝
IN
cores. Actual core loss is independent of core
R
OUT(MAX)
R
0 03
SENSE
−
0 03
SENSE
.
.
V
= V
OUT
U
IN
⎞
⎟
⎠
). Remember, the maximum I
)
⎛
⎜
⎝
MIN
V
INFORMATION
V
OUT
U
IN
could be used in the circuit;
+
+
V
V
D
D
⎞
⎟
⎠
W
U
RIPPLE
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be-
cause they generally lack a bobbin, mounting is more
difficult. However, new designs for surface mount that do
not increase the height significantly are available.
Power MOSFET Selection
An external P-channel power MOSFET must be selected
for use with the LTC1772. The main selection criteria for
the power MOSFET are the threshold voltage V
the “on” resistance R
C
Since the LTC1772 is designed for operation down to low
input voltages, a sublogic level threshold MOSFET (R
guaranteed at V
work close to this voltage. When these MOSFETs are used,
make sure that the input supply to the LTC1772 is less than
the absolute maximum V
The required minimum R
erned by its allowable power dissipation. For applications
that may operate the LTC1772 in dropout, i.e., 100% duty
cycle, at its worst case the required R
where P
temperature dependency of R
given for a MOSFET in the form of a normalized R
temperature curve, but δp = 0.005/°C can be used as an
approximation for low voltage MOSFETs.
In applications where the maximum duty cycle is less than
100% and the LTC1772 is in continuous mode, the R
is governed by:
where DC is the maximum operating duty cycle of the
LTC1772.
RSS
R
R
DS ON
DS ON
and total gate charge.
(
(
P
is the allowable power dissipation and δp is the
)
)
DC
≅
=
( )
100
DC I
GS
%
= 2.5V) is required for applications that
=
OUT
DS(ON)
P
(
I
OUT MAX
P
2
(
GS
1 δ
DS(ON)
+
(
, reverse transfer capacitance
rating, typically 8V.
DS(ON)
p
P
)
)
P
)
of the MOSFET is gov-
2
(
1 δ
. (1 + δp) is generally
+
DS(ON)
p
LTC1772
)
is given by:
GS(TH)
DS(ON)
DS(ON)
DS(ON)
1772fb
7
and
vs