LM5116MH/NOPB National Semiconductor, LM5116MH/NOPB Datasheet - Page 19

• Manufacturer Part Number: LM5116MH/NOPB
• Description: IC CTRLR SYNCH BUCK 20-TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Step-Down (Buck)r

Specifications of LM5116MH/NOPB

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 1.22 ~ 80 V
• Current - Output: 20A
• Frequency - Switching: 50kHz ~ 1MHz
• Voltage - Input: 6 ~ 100 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP Exposed Pad, 20-eTSSOP, 20-HTSSOP
• Dc To Dc Converter Type: Synchronous Buck Controller
• Pin Count: 20
• Input Voltage: 6 to 100V
• Output Voltage: 1.215 to 80V
• Output Current: 3.5A
• Package Type: TSSOP EP
• Mounting: Surface Mount
• Operating Temperature Classification: Automotive
• Operating Temperature (min): -40C
• Operating Temperature (max): 125C
• For Use With: LM5116-12EVAL - BOARD EVALUATION FOR LM5116-12LM5116EVAL - BOARD EVALUATION LM5116
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Lead Free Status / Rohs Status: Compliant
• Other names: LM5116MH

The voltage at the UVLO pin should never exceed 16V when
using an external set-point divider. It may be necessary to
clamp the UVLO pin at high input voltages. For the design
example, R
voltage of 6.6V. If sustained short circuit protection is re-
quired, C
D2 may be installed when using C
MOSFETs
Selection of the power MOSFETs is governed by the same
tradeoffs as switching frequency. Breaking down the losses
in the high-side and low-side MOSFETs is one way to deter-
mine relative efficiencies between different devices. When
using discrete SO-8 MOSFETs the LM5116 is most efficient
for output currents of 2A to 10A. Losses in the power MOS-
FETs can be broken down into conduction loss, gate charging
loss, and switching loss. Conduction, or I
proximately:
Where D is the duty cycle. The factor 1.3 accounts for the
increase in MOSFET on-resistance due to heating. Alterna-
tively, the factor of 1.3 can be ignored and the on-resistance
of the MOSFET can be estimated using the R
perature curves in the MOSFET datasheet. Gate charging
loss, P
tance of the power MOSFETs and is approximated as:
Q
and ‘n’ is the number of MOSFETs. If different types of MOS-
FETs are used, the ‘n’ term can be ignored and their gate
charges summed to form a cumulative Q
differs from conduction and switching losses in that the actual
dissipation occurs in the LM5116 and not in the MOSFET it-
self. Further loss in the LM5116 is incurred as the gate driving
current is supplied by the internal linear regulator. The gate
drive current supplied by the VCC regulator is calculated as:
Where Q
MOSFETs at VGS = VCC. To ensure start-up, I
less than the VCC current limit rating of 15mA minimum when
powered by the internal 7.4V regulator. Failure to observe this
rating may result in excessive MOSFET heating and potential
damage. The I
is powered by VCCX.
Where t
Switching loss is calculated for the high-side MOSFET only.
Switching loss in the low-side MOSFET is negligible because
the body diode of the low-side MOSFET turns on before the
MOSFET itself, minimizing the voltage from drain to source
before turn-on. For this example, the maximum drain-to-
source voltage applied to either MOSFET is 60V. VCC pro-
vides the drive voltage at the gate of the MOSFETs. The
selected MOSFETs must be able to withstand 60V plus any
ringing from drain to source, and be able to handle at least
VCC plus ringing from gate to source. A good choice of MOS-
FET for the 60V input design example is the Si7850DP. It has
an R
g
refer to the total gate charge of an individual MOSFET,
DS(ON)
GC
P
R
DC(LO-MOSFET)
gh
FT
P
, results from the current driving the gate capaci-
and t
DC(HO-MOSFET)
of 20 mΩ, total gate charge of 14nC, and rise and
+ Q
UV2
≥
P
1µF will limit the short circuit power dissipation.
SW
GC
gl
F
= 102kΩ and R
I
GC
represent the gate charge of the HO and LO
are the rise and fall times of the MOSFET.
= 0.5 x V
P
run current may exceed 15 mA when VCC
GC
= V
= n x VCC x Q
= (1 - D) x (I
CC
= D x (I
x (Q
IN
x I
gh
O
UV1
O
+ Q
x (t
2
FT
O
x R
= 21kΩ for a shut-down
2
R
g
gl
with R
x R
) x f
+ t
x f
DS(ON)
SW
F
DS(ON)
g
2
) x f
SW
. Gate charge loss
R loss P
UV1
x 1.3)
SW
DS(ON)
and R
x 1.3)
GC
should be
DC
vs Tem-
UV2
, is ap-
.
19
fall times of 10ns and 12ns respectively. In applications where
a high step-down ratio is maintained for normal operation, ef-
ficiency may be optimized by choosing a high-side MOSFET
with lower Q
For higher voltage MOSFETs which are not true logic level, it
is important to use the UVLO feature. Choose a minimum op-
erating voltage which is high enough for VCC and the boot-
strap (HB) supply to fully enhance the MOSFET gates. This
will prevent operation in the linear region during power-on or
power-off which can result in MOSFET failure. Similar con-
sideration must be made when powering VCCX from the
output voltage. For the high-side MOSFET, the gate threshold
should be considered and careful evaluation made if the gate
threshold voltage exceeds the HO driver UVLO.
MOSFET SNUBBER
A resistor-capacitor snubber network across the low-side
MOSFET reduces ringing and spikes at the switching node.
Excessive ringing and spikes can cause erratic operation and
couple spikes and noise to the output. Selecting the values
for the snubber is best accomplished through empirical meth-
ods. First, make sure the lead lengths for the snubber con-
nections are very short. Start with a resistor value between
5Ω and 50Ω. Increasing the value of the snubber capacitor
results in more damping, but higher snubber losses. Select a
minimum value for the snubber capacitor that provides ade-
quate damping of the spikes on the switch waveform at high
load.
ERROR AMPLIFIER COMPENSATION
R
characteristics to accomplish a stable voltage loop gain. One
advantage of current mode control is the ability to close the
loop with only two feedback components, R
The voltage loop gain is the product of the modulator gain and
the error amplifier gain. For the 5V output design example,
the modulator is treated as an ideal voltage-to-current con-
verter. The DC modulator gain of the LM5116 can be modeled
as:
The dominant low frequency pole of the modulator is deter-
mined by the load resistance (R
(C
For R
then f
DC Gain
For the 5V design example the modulator gain vs. frequency
characteristic was measured as shown in
COMP
OUT
LOAD
P(MOD)
). The corner frequency of this pole is:
, C
(MOD)
COMP
= 5V / 7A = 0.714Ω and C
= 700Hz
g
, and low-side MOSFET with lower R
f
DC Gain
= 0.714Ω / (10 x 10mΩ) = 7.14 = 17dB
P(MOD)
and C
= 1 / (2
HF
(MOD)
configure the error amplifier gain
π
= R
x R
LOAD
LOAD
LOAD
) and output capacitance
/ (A x R
OUT
x C
= 320µF (effective)
Figure
OUT
COMP
S
)
)
www.national.com
and C
11.
DS(ON)
COMP
.
.