LT3825EFE#TRPBF Linear Technology, LT3825EFE#TRPBF Datasheet - Page 11

• Manufacturer Part Number: LT3825EFE#TRPBF
• Description: IC CNTRLR SYNC 16-TSSOP
• Manufacturer: Linear Technology
• Type: Flybackr

Specifications of LT3825EFE#TRPBF

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Frequency - Switching: 50kHz ~ 250kHz
• Voltage - Input: 12 ~ 18 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Power - Output: 60W
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Voltage - Output: -

that developed under these conditions, forced continuous
operation normally occurs. See Applications Information
for further details.
Enable Delay (ENDLY)
The fl yback pulse appears when the primary-side switch
shuts off. However, it takes a fi nite time until the trans-
former primary-side voltage waveform represents the
output voltage. This is partly due to rise time on the pri-
mary-side MOSFET drain node but, more importantly, is
due to transformer leakage inductance. The latter causes
a voltage spike on the primary side, not directly related
to output voltage. Some time is also required for internal
settling of the feedback amplifi er circuitry. In order to
maintain immunity to these phenomena, a fi xed delay is
introduced between the switch turn-off command and the
enabling of the feedback amplifi er. This is termed “enable
delay.” In certain cases where the leakage spike is not
suffi ciently settled by the end of the enable delay period,
regulation error may result. See Applications Information
for further details.
Collapse Detect
Once the feedback amplifi er is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the fl yback
voltage (FB referred) to a fi xed reference, nominally 80%
of V
the feedback amplifi er is disabled.
Minimum Enable Time
The feedback amplifi er, once enabled, stays enabled for
a fi xed minimum time period termed “minimum enable
time.” This prevents lockup, especially when the output
voltage is abnormally low; e.g., during start-up. The mini-
mum enable time period ensures that the V
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. This time is set internally.
Effects of Variable Enable Period
The feedback amplifi er is enabled during only a portion of
the cycle time. This can vary from the fi xed minimum enable
OPERATION
FB
. When the fl yback waveform drops below this level,
C
node is able
time described to a maximum of roughly the “off” switch
time minus the enable delay time. Certain parameters of
feedback amp behavior are directly affected by the variable
enable period. These include effective transconductance
and V
Load Compensation Theory
The LT3825 uses the fl yback pulse to obtain information
about the isolated output voltage. An error source is
caused by transformer secondary current fl ow through
the synchronous MOSFET R
impedances of the transformer secondary and output
capacitor. This was represented previously by the ex-
pression “I
ally more useful to convert this expression to effective
output impedance. Because the secondary current only
fl ows during the off portion of the duty cycle (DC), the
effective output impedance equals the lumped secondary
impedance divided by OFF time DC.
Since the OFF time duty cycle is equal to 1 – DC then:
where:
This impedance error may be judged acceptable in less
critical applications, or if the output load current remains
relatively constant. In these cases the external FB resistive
divider is adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error is minimized by the use of the load compensation
function.
Figure 1 shows the Block Diagram of the load compensation
function. Switch current is converted to a voltage by the
external sense resistor, averaged and lowpass fi ltered by
the internal 50k resistor R
on C
R
a current at the collector of Q3 that is subtracted from the
CMP
R
DC = duty cycle
R
R
S(OUT)
DS(ON)
S OUT
CMP
(
C
resistor by op amp A1 and transistor Q3 producing
node slew rate.
. This voltage is impressed across the external
)
= effective supply output impedance
SEC
and ESR are as defi ned previously
=
ESR R
• (ESR + R
1
+
–
DC
DS ON
(
CMPF
DS(ON)
)
DS(ON)
and the external capacitor
).” However, it is gener-
and real life nonzero
LT3825
11
3825fc