LTC3728LEGN Linear Technology, LTC3728LEGN Datasheet - Page 26

• Manufacturer Part Number: LTC3728LEGN
• Description: IC REG SW DUAL 2PH STPDWN 28SSOP
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3728LEGN

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.8 ~ 7 V
• Current - Output: 3A
• Frequency - Switching: 250kHz ~ 550kHz
• Voltage - Input: 4.5 ~ 28 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIONS INFORMATION
LTC3728L/LTC3728LX
3. I
4. Transition losses apply only to the topside MOSFET(s),
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% effi ciency degradation in portable systems. It is very
important to include these system level losses during the
design phase. The internal battery and fuse resistance
26
Supplying INTV
input from an output-derived source will scale the V
current required for the driver and control circuits by
a factor of (Duty Cycle)/(Effi ciency). For example, in a
20V to 5V application, 10mA of INTV
in approximately 2.5mA of V
mid-current loss from 10% or more (if the driver was
powered directly from V
fuse (if used), MOSFET, inductor, current sense resis-
tor, and input and output capacitor ESR. In continuous
mode the average output current fl ows through L and
R
and the synchronous MOSFET. If the two MOSFETs have
approximately the same R
one MOSFET can simply be summed with the resistances
of L, R
if each R
and R
pacitance losses), then the total resistance is 130mΩ.
This results in losses ranging from 3% to 13% as the
output current increases from 1A to 5A for a 5V output,
or a 4% to 20% loss for a 3.3V output. Effi ciency var-
ies as the inverse square of V
components and output power level. The combined
effects of increasingly lower output voltages and higher
currents required by high performance digital systems
is not doubling, but quadrupling, the importance of loss
terms in the switching regulator system!
and become signifi cant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:
2
Transition Loss =
SENSE
R losses are predicted from the DC resistances of the
ESR
SENSE
, but is “chopped” between the topside MOSFET
DS(ON)
= 40mΩ (sum of both input and output ca-
and ESR to obtain I
= 30mΩ, R
CC
power through the EXTV
( )
(
C
V
IN
MILLER
IN
DS(ON)
) to only a few percent.
2
L
IN
•
= 50mΩ, R
OUT
current. This reduces the
)
I
2
MAX
( )
, then the resistance of
R losses. For example,
f
2
for the same external
5V – V
CC
(
R
current results
SENSE
DR
1
TH
)
•
CC
+
= 10mΩ
switch
V
1
TH
IN
losses can be minimized by making sure that C
equate charge storage and very low ESR at the switching
frequency. A 25W supply will typically require a minimum of
20μF to 40μF of capacitance having a maximum of 20mΩ to
50mΩ of ESR. The LTC3728L 2-phase architecture typically
halves this input capacitance requirement over competing
solutions. Other losses, including Schottky conduction
losses during dead time and inductor core losses, generally
account for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
an amount equal to ΔI
fective series resistance of C
charge or discharge C
signal that forces the regulator to adapt to the current
change and return V
this recovery time, V
overshoot or ringing, which would indicate a stability
problem. OPTI-LOOP compensation allows the transient
response to be optimized over a wide range of output
capacitance and ESR values. The availability of the I
not only allows optimization of control loop behavior but
also provides a DC coupled and AC fi ltered closed loop
response test point. The DC step, rise time and settling
at this test point truly refl ects the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
can also be estimated by examining the rise time at the
pin. The I
circuit will provide an adequate starting point for most
applications.
The I
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
TH
series R
TH
external components shown in the Figure 1
C
-C
C
OUT
OUT
fi lter sets the dominant pole-zero
OUT
LOAD
to its steady-state value. During
can be monitored for excessive
generating the feedback error
(ESR), where ESR is the ef-
OUT
. ΔI
LOAD
also begins to
OUT
IN
shifts by
has ad-
TH
3728lxfe
pin