LTC1159CG Linear Technology, LTC1159CG Datasheet - Page 6

• Manufacturer Part Number: LTC1159CG
• Description: IC SW REG STEP-DWN HI-EFF 20SSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC1159CG

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: Adjustable
• Current - Output: 50mA
• Frequency - Switching: 250kHz
• Voltage - Input: 4 ~ 40 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

FU CTIO AL DIAGRA
OPERATIO
LTC1159
LTC1159-3.3/LTC1159-5
The LTC1159 uses a current mode, constant off-time
architecture to synchronously switch an external pair of
complementary power MOSFETs. Operating frequency is
set by an external capacitor at the C
The output voltage is sensed either by an internal voltage
divider connected to the SENSE
LTC1159-5) or an external divider returned to the V
(LTC1159). A voltage comparator V, and a gain block G,
compare the divided output voltage with a reference volt-
age of 1.25V. To optimize efficiency, the LTC1159 auto-
matically switches between two modes of operation, burst
and continuous.
A low dropout 4.5V regulator provides the operating volt-
age V
start-up. During normal operation, the LTC1159 family
powers the drivers and control from the output via the
EXTV
referenced to ground and drives the N-channel MOSFET
gate directly. The P-channel gate drive must be referenced
to the main supply input V
6
U
CC
CC
EXTV
SHDN2
for the MOSFET drivers and control circuitry during
V
pin to improve efficiency. The N-GATE pin is
CC
IN
U
SLEEP
LOW DROP SWITCH
4.5V REGULATOR
U
LOW DROPOUT
S
+
–
(Refer to Functional Diagram)
V
TH2
IN
, which is accomplished by
C
T
–
CAP
V
pin (LTC1159-3.3 and
W
CC
T
V
TH1
pin.
Internal divider broken at V
550k
CONTROL
–
+
OFF-TIME
Q
T
R
S
FB
SENSE
pin
–
level-shifting the P-drive signal via an internal 550k resistor
and external capacitor.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between the SENSE
and SENSE
series with the inductor. When the voltage across the shunt
reaches its threshold value, the P-gate output is switched
to V
capacitor C
mined by the off-time controller. The discharge current is
made proportional to the output voltage to model the
inductor current, which decays at a rate which is also
proportional to the output voltage. While the timing
capacitor is discharging, the N-gate output is high, turning
on the N-channel MOSFET.
When the voltage on C
tor T trips, setting the flip-flop. This causes the N-gate output
to go low (turning off the N-channel MOSFET) and the P-
gate output to also go low (turning the P-channel MOSFET
back on). The cycle then repeats. As the load current
FB
C
IN
for adjustable versions.
+
–
, turning off the P-channel MOSFET. The timing
I
TH
13k
T
V
–
SGND
25mV TO 150mV
is now allowed to discharge at a rate deter-
pins connected across an external shunt in
+
–
PGND
V
G
CC
T
–
+
has discharged past V
REFERENCE
550k
1.25V
SENSE
P-GATE
P-DRIVE
N-GATE
+
V
OS
SHDN1
V
FB
TH1
SENSE
, compara-
LTC1159 • FD
100k
–
+