LTC3890EGN-1#TRPBF Linear Technology, LTC3890EGN-1#TRPBF Datasheet - Page 25

• Manufacturer Part Number: LTC3890EGN-1#TRPBF
• Description: IC BUCK SYNC ADJ DUAL 28SSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC3890EGN-1#TRPBF

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.8 ~ 24 V
• Frequency - Switching: 350kHz ~ 535kHz
• Voltage - Input: 4 ~ 60 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -

Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ΔI
series resistance of C
discharge C
forces the regulator to adapt to the current change and
return V
time V
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior, but it also provides
a DC coupled and AC filtered closed-loop response test
point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming
a predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin. The
ITH external components shown in Figure 13 circuit will
provide an adequate starting point for most applications.
The ITH series R
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
APPLICATIONS INFORMATION
input capacitance requirement over competing solu-
tions. Other losses including Schottky conduction losses
during dead-time and inductor core losses generally
account for less than 2% total additional loss.
OUT
OUT
can be monitored for excessive overshoot or
OUT
to its steady-state value. During this recovery
generating the feedback error signal that
C
-C
LOAD
C
OUT
filter sets the dominant pole-zero
(ESR), where ESR is the effective
. ΔI
LOAD
also begins to charge or
OUT
shifts by an
Placing a power MOSFET directly across the output ca-
pacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better
to look at the ITH pin signal which is in the feedback loop
and is the filtered and compensated control loop response.
The gain of the loop will be increased by increasing R
and the bandwidth of the loop will be increased by de-
creasing C
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
should be controlled so that the load rise time is limited
to approximately 25 • C
require a 250μs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example for one channel, assume V
12V(nominal), V
V
The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the FREQ pin
to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
LOAD
SENSE(MAX)
ΔI
L
OUT
to C
=
( )
, causing a rapid drop in V
V
f
C
OUT
OUT
. If R
( )
= 75mV and f = 350kHz.
L
is greater than 1:50, the switch rise time
⎛
⎜
⎜
⎝
C
IN
1–
is increased by the same factor that C
= 22V (max), V
V
IN(NOM)
V
LOAD
OUT
. Thus a 10μF capacitor would
⎞
⎟
⎟
⎠
OUT
LTC3890-1
OUT
= 3.3V, I
. No regulator can
MAX
25
= 5A,
38901fa
IN
=
C
C