A8450KLB Allegro Microsystems Inc, A8450KLB Datasheet - Page 10

• Manufacturer Part Number: A8450KLB
• Description: IC REG MULTI-OUT AUTO 24-SOIC
• Manufacturer: Allegro Microsystems Inc
• Type: Step-Down (Buck)r

Specifications of A8450KLB

• Topology: Step-Down (Buck) (1), Linear (LDO) (4)
• Function: Automotive
• Number Of Outputs: 4
• Voltage/current - Output 1: 5.7V, 1.2A
• Voltage/current - Output 2: 5V, 200mA
• Voltage/current - Output 3: 5V, 200mA
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 6 V ~ 45 V
• Operating Temperature: -40°C ~ 135°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Current - Output: 200mA, 550mA
• Voltage - Output: 3.3V, 5V, 5.7V, Adj
• Voltage - Input: 6 ~ 45 V
• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Frequency - Switching: -

A8450
low, ENB acts as a single reset control.
Diagnostics. An open drain output, through the NFAULT pin, is
pulled low to signal to a DSP or microcontroller any of the follow-
ing fault conditions:
• V5A, the 5 V analog regulator output, is shorted to supply
• Either or both of the V5A and the V5D regulator outputs are
• Device junction temperature, T
Charge Pump. The charge pump generates a voltage above V
order to provide adequate gate drive for the N-channel buck switch.
A 0.1 μF ceramic monolithic capacitor, C7, should be connected
between the VCP pin and the VBB pin, to act as a reservoir to run
the buck converter switching regulator.
V
in the case of a fault condition. In addition, a 0.1 μF ceramic mono-
lithic capacitor, C8, should be connected between CP1 and CP2.
Power On Reset Delay. The POR block monitors the supply
voltages and provides a signal that can be used to reset a DSP or
microcontroller. A POR event is triggered by any of the following
conditions:
• Either V33 or VADJ is pulled below its UVLO threshold,
• Both input signal pins, ENB and ENBAT, are pulled low.
below their UVLO threshold, V
threshold, T
V
regulator,
falls below V
This immediately pulls the NPOR pin low, indicating that the
device is beginning a power-off sequence. In addition, the buck
CP
UVLOV33
is internally monitored to ensure that the charge pump is disabled
or
V
OC
JTW
V
REGMON
UVLOVADJ
, is exceeded. It also occurs if the VREG voltage
, due to current exceeding I
. This occurs if the current limit on either
J
UVLOV5
, exceeds the Thermal Warning
Automotive Multioutput Voltage Regulator
DSLIM
.
BB
in
• V
• During any normal power-on, V
An open drain output, through the NPOR pin, is provided to signal a
POR event to the DSP or microcontroller. The reset occurs after an
adjustable delay, t
to the CPOR pin. The value of t
following formula
where C
A POR can be forced without a significant drop in the supply volt-
age, V
However, pulse duration should be short enough so that V
not drop significantly.
Thermal Shutdown. When the device junction temperature, T
is sensed to be at T
temperature, T
same time, a thermal shutdown circuit disables the buck converter,
protecting the A8450 from damage.
converter switching regulator is disabled, and the VREG supply
begins to ramp down. The rate at which V
dent on the total current draw, I
capacitors (C1, C2, C3, and C4).
V
REG
UVLOVADJ
REG
drops below its UVLO threshold,
CPOR
, by pulsing low both the ENB and the ENBAT pins.
, triggering a POR.
(μF) is the value of the C9 capacitor.
JTW
POR
), a fault is indicated at the NFAULT pin. At the
JTSD
, set by an external capacitor, C9, connected
t
POR
(≈15°C higher than the thermal warning
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
= 2.13
LOAD
POR
OUTVADJ
×
10
(ms) is calculated using the
5
, and value of the output
×
V
C
falls below
UVLOVREG
CPOR
REG
decays is depen-
.
REG
does
10
J
,