ISL6529CR Intersil, ISL6529CR Datasheet - Page 10

• Manufacturer Part Number: ISL6529CR
• Description: IC CTRLR PWM DUAL REG 16-QFN
• Manufacturer: Intersil
• Type: Step-Down (Buck)r

Specifications of ISL6529CR

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.5 ~ 4.5 V
• Frequency - Switching: 600kHz
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output: -
• Voltage - Input: -
• Power - Output: -

Modulator Break Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks Z
F
F
LC
ESR
∆
FIGURE 6. VOLTAGE-MODE BUCK CONVERTER
V
=
OSC
=
--------------------------------------- -
2π
---------------------------------------- -
2π
OSC
×
×
V
E/A
L
ESR
1
O
COMPENSATION DESIGN
1
DETAILED COMPENSATION COMPONENTS
ISL6529
×
ERROR
AMP
C
×
COMP
PWM
O
Z
C
+
FB
COMP
-
+
O
INTERNAL 0.8V
REFERENCE
C1
V
FIGURE 7. FIGURE A. SIMPLIFIED DIAGRAM OF THE LINEAR VOLTAGE REGULATOR
REF
C2
-
+
R2
DRIVER
10
0.8V
Z
IN
IN
FB
and Z
FB
AMPLIFIER
Z
ERROR
FB
+
-
ISL6529
V
FB
IN
C3
PHASE
(PARASITIC)
. They provide the
Z
R1
IN
L
C16
OUT
R3
ESR
DRIVE2
C
V
O
OUT
+
ISL6529, ISL6529A
GATE
(EQ. 5)
(EQ. 6)
V
R12
C4
OUT
INPUT VOLTAGE
C
ISS
C
GD
= C
X1
C
DRAIN
GS
GS
link between the modulator transfer function and a
controllable closed loop transfer function of V
goal of component selection for the compensation network is
to provide a loop gain with high 0dB crossing frequency
(f
difference between the closed loop phase at f
degrees .
Compensation Break Frequency Equations
Follow this procedure for selecting compensation
components by locating the poles and zeros of the
compensation network:
+ C
1/gfs
Poles:
Zeros:
1. Set the loop gain (R2/R1) to provide a converter
2. Place the first compensation zero, F
3. Position the second compensation zero, F
4. Locate the first compensation pole, F
5. Position the second compensation pole at half the
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin; repeat if necessary.
0dB
GD
SIMPLIFIED MODEL
bandwidth of one quarter of the switching frequency.
filter double pole (~75% F
output filter double pole, F
filter ESR zero, F
converter switching frequency, F
) and adequate phase margin. Phase margin is the
R5
R6
F
F
F
OF THE MOSFET
F
Z2
P1
P2
Z1
SOURCE
=
R
=
=
=
SAMPLE
------------------------------------------------------ -
2π
------------------------------------------------------ -
2π
-----------------------------------
2π
-----------------------------------
2π
×
×
×
×
(
R
R
R
R1
1
1
2
3
2
×
×
×
+
REGULATED OUTPUT
1
1
ESR


C3
C1
ESR
R3
C1
--------------------- -
C1
C
OUTPUT
)
.
×
+
×
C2
C2
C3
LC


LC
).
.
R
LOAD
SW
Z1
.
P1
, below the output
, at the output
OUT
0dB
Z2
, at the
/V
and 180
April 12, 2005
REF
(EQ. 10)
(EQ. 11)
(EQ. 8)
(EQ. 9)
FN9070.5
. The