LM27212SQX/NOPB National Semiconductor, LM27212SQX/NOPB Datasheet - Page 12

• Manufacturer Part Number: LM27212SQX/NOPB
• Description: IC CURR-MODE BUCK CTRLR 48-LLP
• Manufacturer: National Semiconductor
• Type: Step-Down (Buck)r

Specifications of LM27212SQX/NOPB

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.7 ~ 1.71 V
• Voltage - Input: 5 ~ 30 V
• Operating Temperature: -5°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Power - Output: 1.56W
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Frequency - Switching: -
• Other names: LM27212SQX; LM27212SQXTR

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Operation Description
point where X1 (which is now the same as V- because ih is
zero) is equal to V+, Channel 2’s top switch gets turned on
and ih starts to flow through RH2.
In reality, the steady-state voltage across RR2 is not pure
DC. That complicates the precise calculation of the operating
point. See Design Considerations.
SOFT-START
By charging up the capacitor connected between the SS pin
and ground with a 20µA current, the VREF pin voltage
gradually and linearly increases. That causes the inductor
current to build up, and hence the output voltage will follow
VREF. The required capacitance at the SS pin is simply
20µA divided by the desired output voltage slew rate. For
example, if output voltage needs to go to 1V within 2ms, then
the capacitance required would be about 40nF.
SOFT SHUTDOWN
The LM27212 goes through a soft shutdown process upon
receiving a de-asserted VRON signal. A constant 40µA cur-
rent discharges the soft start capacitor and linearly brings
down the VREF voltage. The output voltage will follow VREF
until VREF is 0.2V, after which the bottom FET is kept on and
the top FET is kept off, causing the output voltage to quickly
drop to zero.
Soft shutdown serves two purposes. One is to prevent a
severe negative output voltage while discharging the output
capacitors during shutdown. The other is so that output
voltage ramps down in a well controlled manner and the
difference between various voltage rails supplying the pro-
cessor can be controlled.
OVER-VOLTAGE PROTECTION
The over-voltage protection trigger level can be set by tying
the VOVP pin to a constant voltage. When the output voltage
exceeds the VOVP pin voltage by 25%, the IC will turn off the
top FET and turn on the bottom FET. The soft start capacitor
will be discharged by the soft shutdown current.
After the VDD pin voltage or VRON is toggled, the IC will go
through a normal soft start.
POWER GOOD FLAG
After the EXT PWRGD signal is asserted at the XPOK pin,
the LM27212 will wait 6ms and then release PGOOD if the
core voltage is within
(VBOOT voltage).
During a Dynamic VID or a mode transition, the PGOOD is
masked for about 130µs and asserted high.
Upon de-assertion of VRON, PGOOD is pulled low within
90ns.
DYNAMIC VID TRANSITIONS
Upon detecting a DAC code change, the LM27212 will blank
the Power Good for about 130µs, during which time the
VREF voltage gradually transitions to the new DAC voltage.
The speed of the transition depends on the soft start capaci-
tor. The current that charges or discharges the soft start
capacitor during such a transition is 350µA typical. The slew
rate of the Dynamic VID change is simply 350µA divided by
SS pin capacitance. For example, if the soft start capacitor is
22nF, then the Dynamic VID slew rate is 16mV/µs.
±
12% of the initial VREF target voltage
(Continued)
12
DIODE EMULATION MODE
In such a mode, the zero-cross detector senses the Vds of
the Channel 1 bottom FET while OUT1 is low. If the sensed
Vds is negative, the bottom FET will remain on. If the sensed
Vds starts to go positive, the bottom FET will be turend off so
that inductor current cannot go negative. This action pre-
vents energy from cycling back from output capacitors to the
power source. This mode enjoys better efficiency than the
pure asynchronous mode because before the inductor cur-
rent goes to zero it flows through FET instead of a diode. By
implementing such a mode, the switching frequency can
drop significantly at light loads. As a result, both the switch-
ing loss and MOSFET gate charge loss can be significantly
reduced.
STOP CPU MODE
During normal operation, if the STP_CPU# pin is asserted
and the SLP pin is not asserted, the VREF pin voltage will
transition to the voltage at the VSTP pin. The speed of the
transition depends on the soft start capacitor. The current
that charges or discharges the soft start capacitor during
such a transition is 350µA typical. The slew rate of the mode
change is simply 350µA divided by SS pin capacitance. For
example, if the soft start capacitor is 22nF, then the output
voltage slew rate is 16mV/µs. Whenever the LM27212 is
entering or exiting the Stop CPU mode, PGOOD is masked
for about 130µs.
SLEEP MODE
The LM27212 will enter the Sleep mode only when both
STP_CPU# and SLP are asserted. Upon assertion of the
Sleep mode, the VREF pin voltage will transition to the
voltage at the VSLP pin. The speed of the transition depends
on the soft start capacitor. The current that charges or dis-
charges the soft start capacitor during such a transition is
350µA typical. The slew rate of the mode change is simply
350µA divided by SS pin capacitance. For example, if the
soft start capacitor is 22nF, then the output voltage slew rate
is 16mV/µs. Whenever the LM27212 is entering or exiting
the Sleep mode, PGOOD is masked for about 130µs.
MODE CHANGE
A mode change is a change in the VREF voltage caused by
entering or existing Stop CPU mode or Sleep mode. During
mode change or a Dynamic VID event, the soft start capaci-
tor is charged or discharged with a 350µA current.
POWER SAVING MODE
When both the DE_EN# and STP_CPU# pins are asserted
and SLP is not toggling, the LM27212 will enter the Power
Saving mode. In such a mode, Channel 1 will operate in
Diode Emulator mode. Channel 2’s status depends on SLP.
If SLP is also asserted, Channel 2 will be turned off (both
OUT2 and SYNC2 will remain low, i.e. all Channel 2 FETs
will be off), and Vcore will go to the VSLP voltage. If SLP is
not asserted, Channel 2 will operate in pure asynchronous
mode in which the bottom FET will not be turned on, and
Vcore will be VID value minus the Stop CPU offset.
If SLP goes from low to high during Power Saving mode, the
LM27212 enforces two-channel synchronous mode for
about 130µs to guarantee Vcore can be pulled down within
the specified time. Refer to the Modes During Normal Op-
eration table.