KSZ8695P Micrel Inc, KSZ8695P Datasheet - Page 11

• Manufacturer Part Number: KSZ8695P
• Description: IC ARM9 W/MMU PHY 10/100 289PBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8695P

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 289-PBGA
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.7/3V
• Operating Supply Voltage (max): 1.9/3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 289
• For Use With: 576-1623 - BOARD EVALUATION KSZ8695P-MMB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1509-5; KSZ8695P

Note:
1. I = Input.
Pin Number
Micrel, Inc.
May 2006
O/I = Output in normal mode; input pin during reset.
O = Output.
I/O = Bidirectional.
G14
G15
M14
M16
M15
P15
R15
A17
A10
D11
C10
N15
F14
F15
F17
F16
L15
L14
R4
U7
U6
R6
R5
U5
M4
B4
B3
B2
T5
P5
T7
T6
P6
F4
URIN/TSTRST
CPUCLKSEL
Pin Name
DBGENN
RESETN
SDCASN
SDCSN1
SDOCLK
SDRASN
SCANEN
SDCSN0
TESTEN
UDCDN/
SDWEN
UCTSN/
UDTRN/
URTSN/
SDICLK
BISTEN
SDQM0
SDQM1
SDQM2
SDQM3
SERRN
UDSRN
RCSN0
RCSN1
REQ1N
REQ2N
REQ3N
STOPN
TRDYN
TRSTN
TEST1
TEST2
TDO
TMS
TCK
TDI
Type
I/O
I/O
O/I
O/I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
(1)
Pin Function
ROM/SRAM/FLASH Chip Select. Active Low.
ROM/SRAM/FLASH Chip Select. Active Low.
PCI Bus Request 1. Active Low. Input for Host Bridge Mode and Guest
Bridge Mode.
PCI Bus Request 2. Active Low. Input for Host Bridge Mode, Not Used in
Guest Bridge Mode.
PCI Bus Request 3. Active Low. Input for Host Bridge Mode, Not Used in
Guest Mode
KS8695P Chip Reset. Active Low.
SDRAM Column Address Strobe. Active Low.
SDRAM Chip Select. Active Low Chip Select Pins for SDRAM.
SDRAM Chip Select. Active Low Chip Select Pins for SDRAM.
SDRAM Clock In.
System/SDRAM Clock Out.
SDRAM Data Input/Output Mask.
SDRAM Data Input/Output Mask.
SDRAM Data Input/Output Mask.
SDRAM Data Input/Output Mask.
SDRAM Row Address Strobe. Active Low.
SDRAM Write Enable. Active Low.
PCI System Error Signal. Active Low.
PCI Stop Signal. Active Low.
JTAG Test Clock.
JTAG Test Data In.
JTAG Test Data Out.
PHY Test Pin (factory reserved test signal).
PHY Test Pin (factory reserved test signal).
Chip Test Enable (factory reserved test signal). Must be connected to GND
for normal operation.
JTAG Test Mode Select.
PCI Target Ready Signal. Active Low.
JTAG Test Reset. Active Low.
UART Data Set Ready. Active Low. BIST Enable (factory reserved test
signal).
UART Data Carrier Detect. Scan Enable (factory reserved test signal).
UART Data Set Ready. Active Low.
UART Data Terminal Ready. Active Low. Debug Enable (factory reserved
test signal).
UART Ring Indicator/Chip Test Reset (factory reserved test signal).
UART Request to Send/CPU Clock Select.
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M9999-051806
KS8695P