KSZ8695P Micrel Inc, KSZ8695P Datasheet - Page 16

• Manufacturer Part Number: KSZ8695P
• Description: IC ARM9 W/MMU PHY 10/100 289PBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8695P

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 289-PBGA
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.7/3V
• Operating Supply Voltage (max): 1.9/3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 289
• For Use With: 576-1623 - BOARD EVALUATION KSZ8695P-MMB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1509-5; KSZ8695P

Switch Engine
• 5-Port 10/100 integrated switch with one WAN and four LAN physical layer transceivers
• 16Kx32 on-chip SRAM for frame buffering
• 1.4Gbps on-chip memory bandwidth for wire-speed frame switching
• 10Mbps and 100Mbps modes of operation for both full and half duplex
• Supports 802.1Q tag-based VLAN and port-based VLAN
• Supports 8.2,1p-based priority, DiffServ priority, and post-based priority
• Integrated address look-up engine, supports 1K absolute MAC addresses
• Automatic address learning, address aging, and address migration
• Broadcast storm protection
• Full-duplex IEEE 802.3x flow control
• Half-duplex back pressure flow control
• Supports IGMP snooping
• Spanning Tree Protocol support
Advanced Memory Controller Features
• Supports glueless connection to two banks of ROM/SRAM/FLASH memory with programmable 8/16/32 bit data bus and
• Supports glueless connection to two SDRAM banks with programmable 8/16/32-bit data bus and programmable
• Supports three external I/O banks with programmable 8/16/32-bit data bus and programmable access timing
• Programmable system clock speed for power management
• Automatic address line mapping for 8/16/32-bit accesses on Flash, ROM, SRAM, and SDRAM interfaces
Direct Memory Access (DMA) Engines
• Independent MAC DMA engine with programmable burst mode for WAN port
• Independent MAC DMA engine with programmable burst mode for LAN ports
• Supports little-endian byte ordering for memory buffers and descriptors
• Contains large independent receive and transmit FIFOs (3KB receive/3KB transmit) for back-to-back packet receive,
• Data alignment logic and scatter gather capability
Protocol Engine and XceleRouter™ Technology
• Supports IPv4 IP header/TCP/UDP packet checksum generation for host CPU offloading
• Supports IPv4 packet filtering based on checksum errors
Network Interface
• Features five MAC units and five PHY units
• Supports 10BASE-T and 100BASE-TX on all LAN ports and one WAN port. Also supports 100BASE-FX on the WAN
• Supports automatic CRC generation and checking
• Supports automatic error packet discard
• Supports IEEE 802.3 auto-negotiation algorithm of full-duplex and half-duplex operation for 10Mbps and 100Mbps
• Supports full-/half-duplex operation on PHY interfaces
• Fully compliant with IEEE 802.3 Ethernet standards
• IEEE 802.3 full-duplex flow control and half-duplex backpressure collision flow control
• Supports MDI/MDI-X auto-crossover
Micrel, Inc.
May 2006
programmable access timing
RAS/CAS latency
and guaranteed no under-run packet transmit
port and on one LAN port
16
M9999-051806
KS8695P