MAX1329BETL+ Maxim Integrated Products, MAX1329BETL+ Datasheet - Page 28

• Manufacturer Part Number: MAX1329BETL+
• Description: IC DAS 12BIT 300KSPS 40-TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1329BETL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
The MAX1329/MAX1330 provide two uncommitted SPDT
switches that can also be configured as a double-
pole/single-throw (DPST) switch (see Tables 28 and 29).
Each switch has a typical on-resistance of 115Ω at AV
= 3V. The switch is controlled through the Switch Control
register or a DPIO configured to control the switches.
The MAX1329/MAX1330 include a 12-bit SAR ADC with
a programmable-gain amplifier (PGA), input multiplex-
er, and digital post-processing. The analog input signal
feeds into the differential input multiplexer and then into
the PGA with gain settings of 1, 2, 4, or 8. The tempera-
ture sensor and supply voltage measurements bypass
the PGA. Both unipolar and bipolar transfer functions
are selectable.
The ADC done status bit (ADD in the Status register)
can be programmed to provide an interrupt. Any of the
DPIOs can be configured as a CONVST input to directly
control the acquisition time and synchronize the conver-
sions. A 16-word FIFO stores the ADC results until the
12-bit data is read by the external µC.
The MAX1329/MAX1330 provide two external analog
inputs: AIN1 and AIN2. The inputs are rail-to-rail and
can be used differentially or single-ended to ground.
The analog inputs can also be used for remote temper-
ature sensing with external diodes.
AIN1 and AIN2 feed directly into a differential multiplexer.
This 16-channel multiplexer is segmented into an upper
and a lower multiplexer (see Tables 7 and 8 for configu-
ration).
The ADC writes its results in the ADC FIFO, which stores
up to sixteen 16-bit words. Each 16-bit word in the FIFO
includes a 4-bit FIFO address and the 12-bit data result
from the ADC. The ADC FIFO includes four pointers:
depth, interrupt, write, and read configured by writing to
the ADC FIFO register (see Figure 4).
A depth pointer sets the working depth of the FIFO such
that locations beyond the depth pointer are inaccessible
for writing or reading. The interrupt pointer sets the loca-
tion that causes an interrupt every time data has been
written to that location. Set the interrupt pointer to the
same or lower location than the depth pointer. The inter-
rupt pointer is set equal to the depth pointer if written
with a value greater than the depth pointer. A write to the
ADC FIFO register causes the write and read pointers to
reset to location 0. Setting the depth pointer to location 0
disables the FIFO.
Single-Pole/Double-Throw (SPDT) Switches
28
______________________________________________________________________________________
Analog-to-Digital Converter (ADC)
ADC FIFO Register
Analog Inputs
DD
Every time a conversion completes, the data is written to
the present location of the write pointer, which then incre-
ments by 1. The write pointer continues to increment until
the depth pointer location has been written. The write
pointer then moves to location 0 and continues to incre-
ment but must remain behind the read pointer. Once the
last valid FIFO location has been written, no further ADC
results are written to the FIFO until the next FIFO location
is cleared by a read.
When the ADC FIFO is enabled, the read pointer points
to location 0. When a read occurs, the pointer then
increments by 1 only if 15 of the 16 bits are clocked out
successfully. Reading the FIFO is done in 16-bit words
consecutively as long as a serial clock is present. The
read pointer must stay one location behind the write
pointer. When the write pointer is one location ahead of
the read pointer and the read continues, it clocks out
the current read location over and over again until the
write pointer increments.
The FIFO can be accessed simultaneously by the serial
interface to read a result and by the ADC to write a
result, but the read and write pointers are never at the
same address.
The accumulator is used for oversampling. In this mode,
up to 256 samples are accumulated in the ADC
Accumulator register. This is a 24-bit read register with
1 bit for dither enable, 3 bits for the accumulator count,
and 20 bits for the accumulated ADC conversions. The
Figure 4. ADC FIFO
DEPTH POINTER
WRITE POINTER
ADC Accumulator, Decimation, and Dither Mode
ADC FIFO
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
READ POINTER
INTERRUPT POINTER