DS34T101GN+ Maxim Integrated Products, DS34T101GN+ Datasheet - Page 9
![IC TDM OVER PACKET 484TEBGA](/photos/6/89/68901/484-bga_exp_pad_sml.jpg)
DS34T101GN+
Manufacturer Part Number
DS34T101GN+
Description
IC TDM OVER PACKET 484TEBGA
Manufacturer
Maxim Integrated Products
Type
TDM (Time Division Multiplexing)r
Datasheet
1.DS34T108GN.pdf
(16 pages)
Specifications of DS34T101GN+
Applications
Data Transport
Mounting Type
Surface Mount
Package / Case
484-BGA Exposed Pad, 484-eBGA, 484-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Jitter Attenuator
Framer/Formatter
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
T1 DSX-1 line build-outs
T1 CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB
E1 waveforms include G.703 waveshapes for both 75 coax and 120 twisted-pair cables
Several local and remote loopback options including simultaneous local and remote
Analog loss of signal detection
AIS generation independent of loopbacks
Alternating ones and zeros generation
Receiver power-down
Transmitter power-down
Transmitter short-circuit limiter with current limit exceeded indication
Transmit open-circuit-detected indication
Crystal-less jitter attenuator with programmable buffer depth (16, 32, 64 or 128 bits)
Can be placed in either the receive path or the transmit path or disabled
Limit trip indication
Fully independent transmit and receive functionality
Full receive and transmit path transparency
T1 SF and ESF framing formats per T1.403, and expanded SLC-96 support (TR-TSY-008).
E1 FAS framing, CRC-4 multiframe per G.704/G.706, and G.732 CAS multiframe
Transmit-side synchronizer
Transmit midpath CRC recalculate (E1)
Detailed alarm and status reporting with optional interrupt support
Large path and line error counters
T1 Idle Code Generation on a per-channel basis in both transmit and receive paths
ANSI T1.403-1999 support
G.965 V5.2 link detect
Ability to monitor one DS0 channel in both the transmit and receive paths
In-band repeating pattern generators and detectors for loop-up and loop-down codes
Bit Oriented Code (BOC) support
Software and hardware signaling support
Interrupt generation on change of signaling data
Optional receive signaling freeze on loss-of-frame, loss-of-signal, or frame slip
Hardware pins provided to indicate loss-of-frame (LOF) or loss-of-signal (LOS)
Automatic RAI generation to ETS 300 011 specifications
RAI-CI and AIS-CI support
Expanded access to Sa and Si bits
Option to extend carrier loss criteria to a 1ms period as per ETS 300 233
Japanese J1 support
T1: BPV, CV, CRC-6 and framing bit errors
E1: BPV, CV, CRC-4, E-bit and frame alignment errors
Timed or manual counter update modes
User defined code generation
Digital Milliwatt code generation
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