KSZ8995MA Micrel Inc, KSZ8995MA Datasheet - Page 40

• Manufacturer Part Number: KSZ8995MA
• Description: IC SWITCH 10/100 5PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8995MA

• Data Rate: 100Mbps
• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• No. Of Ports: 5
• Ethernet Type: IEEE 802.3u
• Supply Voltage Range: 1.7V To 1.9V, 3.15V To 3.45V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: QFP
• No. Of Pins: 128
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Interface Type: MII, SNI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1607 - BOARD EVAL EXPERIMENT KSZ8995MA
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1039

KS8995MA
M9999-051305
Address
Register 2 (0x02): Global Control 0
7
6-4
3
2
1
0
Register 3 (0x03): Global Control 1
7
6
5
4
3
Name
Reserved
802.1p Base Priority
Enable PHY MII
Buffer Share Mode
UNH Mode
Link Change Age
Pass All Frames
Reserved
IEEE 802.3x Transmit
Flow Control Disable
IEEE 802.3x Receive
Flow Control Disable
Frame Length Field Check 1, will check frame length field in the IEEE packets
Description
Reserved.
Used to classify priority for incoming 802.1q packets
“User priority” is compared against this value
⊕ : classified as high priority.
< : classified as low priority.
1, enable PHY MII interface.
Note: if not enabled, the switch will tri-state all outputs.
1, buffer pool is shared by all ports. A port can use
more buffer when other ports are not busy.
0, a port is only allowed to use 1/5 of the buffer pool.
1, the switch will drop packets with 0x8808 in T/L
filed, or DA=01-80-C2-00-00-01.
0, the switch will drop packets qualified as “flow control”
packets.
1, link change from “link” to “no link” will cause fast
aging (<800µs) to age address table faster. After an
age cycle is complete, the age logic will return to
normal (300 + 75 seconds ). Note: If any port is
unplugged, all addresses will be automatically aged
out.
1, switch all packets including bad ones. Used solely
for debugging purpose. Works in conjunction with
sniffer mode.
Reserved.
0, will enable transmit flow control based on AN result.
1, will not enable transmit flow control regardless of
AN result.
0, will enable receive flow control based on AN result.
1, will not enable receive flow control regardless of
AN result.
Note: Bit 5 and bit 4 default values are controlled by
the same pin, but they can be programmed
independently.
If the actual length does not match, the packet will be
dropped (for L/T <1500) .
40
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0x0
0x4
Pin LED[5][1]
strap option.
Pull-down (0):
isolate. Pull-up
(1): Enable.
Note: LED[5][1]
has internal
pull-up.
0x1
0
0
0
0
Pin PMRXD3
strap option.
Pull-down(0):
Enable Tx flow
control. Pull-up(1):
Disable Tx/Rx
flow control.
Note: PMRXD3
has internal pull-
down.
Pin PMRXD3 strap
option. Pull-down
(0): Enable Rx flow
control. Pull-up (1):
Disable Tx/Rx flow
control.
Note: PMRXD3
has internal pull-
down.
0
Micrel, Inc.
May 2005