DS1875T+ Maxim Integrated Products, DS1875T+ Datasheet - Page 26

• Manufacturer Part Number: DS1875T+
• Description: IC SFP CTRLR/TRIPLEXER 38-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of DS1875T+

• Applications: Fiber Optics
• Interface: I²C
• Voltage - Supply: 2.85 V ~ 3.9 V
• Package / Case: *
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PON Triplexer and SFP Controller
than the PWM DAC level, the error amplifier increases
the level on the COMP pin. The level on the COMP pin
is compared to the signal from the oscillator and ramp
generator to set the duty cycle that is input to the gate
driver and maximum duty-cycle limiting block. An
increase on the COMP pin increases the duty cycle.
Conversely, if FB is greater than the PWM DAC, the
level on COMP is decreased, decreasing the duty
cycle. The gate driver and maximum duty-cycle block
is used to limit the maximum duty cycle of the PWM
controller to 90%. This block also disables the PWM dri-
ver if an M3QT has resulted from the APD current
exceeding a desired limit.
The output from the PWM DAC is used to control the
output voltage of the DC-DC converter. The values for
the PWM DAC are recalled from the Table 07h, which is
a temperature-indexed LUT. The temperature-indexed
value from the LUT is written to the PWM DAC register
(Table 02h, Register FEh), which updates the setting of
the PWM DAC. The PWM DAC can also be operated in
a manual mode by disabling the automatic updating
from the LUT. This is done by clearing the PWM EN bit
(Table 02h, Register 80h, Bit 5). The PWM DAC full-
scale output is 1.25V with 8 bits of resolution. When
designing the feedback for the DC-DC converter sec-
tion, the user needs to make sure that the desired level
applied to the FB pin is in this range.
The COMP pin is driven by the error amplifier compar-
ing the PWM DAC to the DC-DC converter feedback
signal at the FB pin. The error amplifier can sink and
source 10µA. An external resistor and capacitor con-
nected to the COMP pin determine the rate of change
the COMP pin. The resistor provides an initial step
when the current from the error amplifier changes. The
capacitor determines how quickly the COMP pin
charges to the desired level. The COMP pin has inter-
nal voltage clamps that limit the voltage level to a mini-
mum of 0.8V and a maximum of 2.1V.
The oscillator and ramp generator create a ramped sig-
nal. The frequency of this signal can be 131.25kHz,
262.5kHz, 525kHz, or 1050kHz and is set by the
PWM_FR[1:0] bits (Table 02h, Register 88h, Bits 5:4).
The low level and high level for the ramped signal are
approximately 1.0V and 1.9V, respectively.
The ramped signal is compared to the voltage level on
the COMP pin to determine the duty cycle that is input
to the gate driver and duty-cycle limiting block. When
COMP is clamped low at 0.8V, below the level of the
ramped signal, the comparator outputs a 0% duty-
cycle signal to the gate driver block. When COMP is
clamped at 2.1V, above the level of the ramped signal,
26
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the comparator outputs a 100% duty-cycle signal to the
gate driver and duty-cycle limiting block. The duty-
cycle liming block is used to limit the duty cycle of the
PWM signal from the SW pin to 90%.
The PWM controller is designed to protect expensive
APDs against adverse operating conditions while pro-
viding optimal bias. The PWM controller monitors photo-
diode current to protect APDs under avalanche
conditions using the MON3 quick trip. A voltage level
that is proportional to the APD current can be input to
the MON3 pin. When this voltage exceeds the level set
by the M3QT DAC (Table 02h, Register C3h), pulses
from the PWM controller are blocked until the fault is
cleared. The quick trip can also toggle the digital output
D2. D2 can be connected to an external FET to quickly
discharge the DC-DC converter filter capacitors.
Optimum inductor selection depends on input voltage,
output voltage, maximum output current, switching fre-
quency, and inductor size. Inductors are typically spec-
ified by their inductance (L), peak current (IPK), and
resistance (LR).
The inductance value is given by:
Where:
V
V
I
T = Time period of switching frequency (seconds)
D = Duty cycle
η = Estimated power conversion efficiency
The equation for inductance factors in conversion effi-
ciency. For inductor calculation purposes, an η of 0.5
to 0.75 is usually suitable.
For example, to obtain an output of 80V with a load cur-
rent of 1.0mA from an input voltage of 5.0V using the
maximum 90% duty cycle and frequency of 1050kHz
(T = 952ns), and assuming an efficiency of 0.5, the pre-
vious equation yields an L of 120µH, so a 100µH induc-
tor would be a suitable value.
The peak inductor current is given by:
OUT(MAX)
IN
OUT
= DC-DC converter input voltage
= Output of DC-DC converter
= Maximum output current delivered
L
=
I
PK
2
V
I
OUT MAX
IN
=
2
V
(
×
IN
D
×
2
L
)
D T
×
×
×
T
V
×
OUT
Inductor Selection
η