KS8842-16MQL Micrel Inc, KS8842-16MQL Datasheet - Page 67
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KS8842-16MQL
Manufacturer Part Number
KS8842-16MQL
Description
IC SWITCH 10/100 16BIT 128PQFP
Manufacturer
Micrel Inc
Specifications of KS8842-16MQL
Applications
*
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Number Of Primary Switch Ports
2
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog/Digital
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.5V
Operating Supply Voltage (min)
3.1V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
KS8842-PMQL-EVAL - EVAL KIT EXPERIMENTAL KS8842KS8842-16MQL-EVAL - EVAL KIT EXPERIMENTAL KS8842
Lead Free Status / RoHS Status
Not Compliant, Lead free / RoHS Compliant
Other names
576-1458
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Bank 17 TXQ Command Register (0x00): TXQCR
This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in the
TXQ memory is queued for transmit.
Bank 17 RXQ Command Register (0x02): RXQCR
This register is programmed by the Host CPU to issue release command to the RXQ. The current frame in the RXQ frame
buffer is read out by the host and the memory space is released.
Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR
The value of this register determines the address to be accessed within the TXQ frame buffer. When the AUTO increment
is set, It will automatically increment the pointer value on Write accesses to the data register.
The counter is incremented by one for every byte access, by two for every word access, and by four for every double
word access.
Micrel, Inc.
Bit
15-1
0
Bit
15-1
0
Bit
15
14
13-11
10-0
October 2007
Default Value
-
0x0
Default Value
-
0x0
Default Value
-
0x0
-
0x0
R/W
RO
RW
R/W
RO
RW
R/W
RO
RW
RO
RW
Description
Reserved
TXETF Enqueue TX Frame
When this bit is set as 1, the current TX frame prepared in the TX buffer is queued for
transmit.
Note: This bit is self-clearing after the frame is finished transmitting. The software
should wait for the bit to be cleared before setting up another new TX frame.
Description
Reserved Do not write to this register.
RXRRF Release RX Frame
When this bit is set as 1, the current RX frame buffer is released.
Note: This bit is self-clearing after the frame memory is released. The software should
wait for the bit to be cleared before processing new RX frames.
Description
Reserved
TXFPAI TX Frame Data Pointer Auto Increment
When this bit is set, the TX Frame data pointer register increments automatically on
accesses to the data register. The increment is by one for every byte access, by two
for every word access, and by four for every doubleword access.
When this bit is reset, the TX frame data pointer is manually controlled by user to
access the TX frame location.
Reserved
TXFP TX Frame Pointer
TX Frame Pointer index to the Frame Data register for access.
This field reset to next available TX frame location when the TX Frame Data has been
enqueued through the TXQ command register.
67
KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9