ADUM1410BRWZ Analog Devices Inc, ADUM1410BRWZ Datasheet - Page 6

• Manufacturer Part Number: ADUM1410BRWZ
• Description: IC ISOLATOR DGTL 4CH UNI 16-SOIC
• Manufacturer: Analog Devices Inc
• Series: iCoupler®r

Specifications of ADUM1410BRWZ

• Propagation Delay: 30ns
• Inputs - Side 1/side 2: 4/0
• Number Of Channels: 4
• Isolation Rating: 2500Vrms
• Voltage - Supply: 2.7 V ~ 5.5 V
• Data Rate: 10Mbps
• Output Type: Logic
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Operating Temperature: -40°C ~ 105°C
• No. Of Channels: 4
• Supply Current: 8.8mA
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: SOIC
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +105°C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 105C
• Package Type: SOIC W
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuM1410/ADuM1411/ADuM1412
Parameter
SWITCHING SPECIFICATIONS
1
2
3
4
5
6
7
8
9
on per-channel supply current for unloaded and loaded conditions. See the
for a given data rate.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t
measured from the 50% level of the rising edge of the V
t
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
|CM
Input enable time is the duration from when V
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the P
See Figure through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure
Figure 15
within the recommended operating conditions.
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
PHL
PSK
ADuM141xARWZ
ADuM141xBRWZ
All Models
propagation delay is measured from the 50% level of the falling edge of the V
is the magnitude of the worst-case difference in t
H
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching,
Channel-to-Channel Matching,
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
Common-Mode Transient Immunity
Refresh Rate
Input Enable Time
Input Disable Time
Input Dynamic Supply Current
Output Dynamic Supply Current
| is the maximum common-mode voltage slew rate that can be sustained while maintaining V
Opposing-Directional Channels
Change vs. Temperature
Codirectional Channels
at Logic High Output
at Logic Low Output
per Channel
per Channel
for total V
8
DD1
9
9
and V
4
8
4
8
DD2
3
3
2
2
supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.
7
7
5
5
PLH
PLH
6
− t
− t
PHL
6
PHL
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
|
|
4
4
6
DISABLE
is set low until the output states are guaranteed to match the input states in the absence of any input data logic
PHL
Symbol
PW
t
PWD
t
t
PW
t
PWD
t
t
t
t
|CM
|CM
f
t
t
I
I
r
DDI (D)
DDO (D)
PHL
PSK
PSKCD/OD
PHL
PSK
PSKCD
PSKOD
R
ENABLE
DISABLE
or t
Ix
/t
signal to the 50% level of the rising edge of the V
, t
, t
F
H
L
PLH
|
|
PLH
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
Rev. H | Page 6 of 24
Min
1
20
10
20
25
25
Power Consumption
Ix
signal to the 50% level of the falling edge of the V
Typ
75
40
5
2.5
35
35
1.1
2.0
5.0
0.07
0.02
section for guidance on calculating the per-channel supply current
O
> 0.8 V
Max
1000
100
40
50
50
100
60
5
30
5
6
Ox
DD2
2
signal.
logic state (see Table 14).
. |CM
L
| is the maximum common-mode voltage slew rate
Unit
ns
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
kV/μs
kV/μs
Mbps
μs
μs
mA/
Mbps
mA/
Mbps
Figure 8
Test Conditions
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
V
transient magnitude = 800 V
V
transient magnitude = 800 V
V
V
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Ix
Ix
IA
IA
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
, V
, V
= V
= 0 V, V
through
Ox
IB
IB
, V
, V
DD1
signal. t
ower Consumption
IC
IC
or V
, V
, V
CM
Figure 10
ID
ID
= 1000 V,
PLH
DD2
= 0 V or V
= 0 V or V
propagation delay is
, V
DISABLE
CM
for information
11
= 1000 V,
is set high
DD1
DD1
through
section.