HCPL-314J-500E Avago Technologies US Inc., HCPL-314J-500E Datasheet - Page 13

• Manufacturer Part Number: HCPL-314J-500E
• Description: OPTOCOUPLER 2CH 0.6A 16-SOIC
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-314J-500E

• Voltage - Isolation: 3750Vrms
• Number Of Channels: 2, Unidirectional
• Propagation Delay High - Low @ If: 300ns @ 8mA
• Current - Dc Forward (if): 25mA
• Input Type: DC
• Output Type: Open Collector
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.50mm Width)
• No. Of Channels: 2
• Optocoupler Output Type: Gate Drive
• Input Current: 12mA
• Output Voltage: 30V
• Opto Case Style: SOIC
• No. Of Pins: 16
• Propagation Delay Low-high: 0.7µs
• Isolation Voltage: 3.75kV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CMR with the LED On (CMR
A high CMR LED drive circuit must keep the LED on dur-
ing common mode transients. This is achieved by over-
driving the LED current beyond the input threshold so
that it is not pulled below the threshold during a tran-
sient. A minimum LED current of 8 mA provides ade-
quate margin over the maximum I
10 kV/μs CMR.
CMR with the LED Off (CMR
A high CMR LED drive circuit must keep the LED off (V
V
during a -dV
flowing through C
V
developed across the logic gate is less than V
LED will remain off and no common mode failure will oc-
cur.
The open collector drive circuit, shown in Figure 24, can
not keep the LED off during a +dV
all the current flowing through C
by the LED, and it is not recommended for applications
requiring ultra high CMR
drive circuit which like the recommended application
circuit (Figure 19), does achieve ultra high CMR perfor-
mance by shunting the LED in the off state.
13
F(OFF)
SAT
of the logic gate. As long as the low state voltage
) during common mode transients. For example,
CM
/dt transient in Figure 23, the current
LEDP
H
L
)
)
also flows through the R
1
performance. The alternative
LEDN
FLH
CM
/dt transient, since
of 5 mA to achieve
must be supplied
F(OFF)
SAT
and
the
F
≤
IPM Dead Time and Propagation Delay Specifications
The HCPL-314J includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time high and low side power transistors are off.
Any overlap in Ql and Q2 conduction will result in large
currents flowing through the power devices from the
high-voltage to the low-voltage motor rails. To minimize
dead time in a given design, the turn on of LED2 should
be delayed (relative to the turn off of LED1) so that un-
der worst-case conditions, transistor Q1 has just turned
off when transistor Q2 turns on, as shown in Figure 26.
The amount of delay necessary to achieve this condition
is equal to the maximum value of the propagation de-
lay difference specification, PDD max, which is specified
to be 500 ns over the operating temperature range of
-40° to 100°C.
Delaying the LED signal by the maximum propaga-
tion delay difference ensures that the minimum dead
time is zero, but it does not tell a designer what the
maximum dead time will be. The maximum dead
time is equivalent to the difference between the
maximum and minimum propagation delay differ-
ence specification as shown in Figure 27. The maxi-
mum dead time for the HCPL-314J is 1 μs (= 0.5 μs
- (-0.5 μs)) over the operating temperature range of
- 40°C to 100°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other
and are switching identical IGBTs.