HCPL-560K-100 Avago Technologies US Inc., HCPL-560K-100 Datasheet - Page 6
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HCPL-560K-100
Manufacturer Part Number
HCPL-560K-100
Description
ISOLAT 1.5KVDC 1CH OPEN 8SMD BJ
Manufacturer
Avago Technologies US Inc.
Datasheet
1.HCPL-5600.pdf
(12 pages)
Specifications of HCPL-560K-100
Package / Case
8-SMD Butt Joint
Voltage - Isolation
1500VDC
Number Of Channels
1, Unidirectional
Current - Output / Channel
25mA
Data Rate
10Mbps
Propagation Delay High - Low @ If
55ns @ 13mA
Current - Dc Forward (if)
20mA
Input Type
DC
Output Type
Open Collector
Mounting Type
Surface Mount
Maximum Continuous Output Current
25 mA
Maximum Fall Time
40 ns
Maximum Forward Diode Current
20 mA
Maximum Rise Time
90 ns
Output Device
Logic Gate Photo IC
Configuration
1 Channel
Maximum Baud Rate
10 MBps
Maximum Forward Diode Voltage
1.9 V
Maximum Reverse Diode Voltage
5 V
Maximum Power Dissipation
200 mW
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Absolute Maximum Ratings
No derating required up to +125°C.
*Selection for higher output voltages up to 20 V is available
Single Channel Product Only
8 Pin Ceramic DIP Single Channel Schematic
ESD Classification
(MIL-STD-883, Method 3015)
Recommended Operating Conditions
*Meets or exceeds DSCC SMD and JEDEC requirements.
6
Parameter
Storage Temperature
Operating Temperature
Case Temperature
Junction Temperature
Lead Solder Temperature
Peak Forward Input Current
(each channel, ≤1 ms duration)
Average Input Forward Current (each channel)
Input Power Dissipation (each channel)
Reverse Input Voltage (each channel
Supply Voltage (1 minute maximum)
Output Current (each channel)
Output Voltage (each channel)
Output Power Dissipation (each channel)
Package Power Dissipation (each channel)
Enable Input Voltage
HCPL-5600/01/0K
6N134, 6N134/883B, HCPL-5630/31/3K, HCPL-5650/51, HCPL-6630/31/3K and HCPL-6650/51/5K
Parameter
Input Current, Low Level, Each Channel
Input Current, High Level, Each Channel*
Supply Voltage, Output
Fan Out (TTL Load) Each Channel
Symbol
I
I
V
N
FL
FH
CC
Note enable pin 7. An external 0.01 µF to 0.1 µF bypass capacitor must
be connected between V
V
Symbol
T
T
T
T
I
I
V
V
I
V
P
P
F(PEAK)
F(AVG)
O
E
A
S
C
J
R
CC
O
O
D
Min.
0
10
4.5
Min.
-65
-55
CC
and ground for each package type.
Max.
+150
+125
+170
+175
260 for 10 sec
40
20
35
5
7.0
25
7*
40
200
5.5
Max.
250
20
5.5
6
(D), Class 1
(Dot), Class 3
Units
µA
mA
V
Units
°C
°C
°C
°C
°C
mA
mA
mW
V
V
mA
V
mW
mW
V