SMS512DFA5E NUMONYX, SMS512DFA5E Datasheet

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... Write protect feature using mechanical switch Built-in write protection features (permanent and temporary) MicroSD packages – ECOPACK – Halogen free – Antimony free Speed class Package form factor 2 2 MicroSD 4 Rev 2 SMSxxxDF Preliminary Data MicroSD ® compliant Operating voltage range 2 3.6 V 1/60 www.numonyx.com 1 ...

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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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SMSxxxDF 6 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Contents 7.4.4 7.4.5 7.5 Clearing status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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SMSxxxDF List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures List of figures Figure 1. Write protection hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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SMSxxxDF 1 Description The secure digital memory card (SD memory card flash-based memory card specifically designed to meet the security, capacity, performance and environmental requirements of the latest-generation audio and video consumer electronic devices, that is ...

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Description Table 3. Power consumption Standby Read Write ° Table 4. Environmental specifications Environmental specifications Temperature Humidity (non-condensing) Contact pads ESD protection Salt water spray Vibration (peak-to-peak) Shock Drop Bending UV light exposure ...

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SMSxxxDF 2 Memory array partitioning The basic unit of data transfer to/from the SD memory card is the byte. The memory array is divided into several structures as described below and summarized in array structures. 2.1 Block The block is ...

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Memory array partitioning Figure 1. Write protection hierarchy Memory card 10/60 Write protect group 0 Sector 1 Block 1 Block 2 Sector 2 Sector 3 Write protect group 1 Write protect group 2 SMSxxxDF ai10041 ...

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SMSxxxDF 3 Secure digital memory card interface This section applies to the MicroSD card when used with an adapter. The secure digital memory card has an advanced 9-pin communication interface (clock, command, 4 data pins and 3 power supply pins) ...

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Secure digital memory card interface Figure 3. MicroSD pin assignment Table 9. MicroSD contact pad assignment Pin Name Type 1 DAT2 CD/ CMD CLK DAT0 8 DAT1 1. ...

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SMSxxxDF 3.1 Secure digital memory card bus topology The secure digital memory card system defines two alternative communications protocols: SD and SPI that correspond to two operating modes. Either mode can be selected in the application, mode selection is transparent ...

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Secure digital memory card interface Figure 4. Secure digital memory card system bus topology 1. DAT1 and DAT2 not connected. 3.2 SD bus protocol Communication over the SD bus is based on command and data bit streams which are initiated ...

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SMSxxxDF Data transfer can be configured by the host to use single or multiple data lines (provided that the card supports this feature). A busy signal on DAT0 is used to indicate that a block write operation is ongoing (see ...

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Secure digital memory card interface Figure 7. (Multiple) block write operation from host to card CMD Command DAT Figure 8. Command token format Transmitter bit '1' = command from host Start bit always '0' Figure 9. Response token format Transmitter ...

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SMSxxxDF Figure 10. Data packet format Start bit always '0' Standard bus (only DAT0 used) Start bit always '0' DAT3 DAT2 Wide bus (all four data lines used) DAT1 DAT0 3.3 SD memory card functional description All communications between the ...

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Secure digital memory card interface Table 10. Card states vs. operation modes Inactive state Idle state Ready state Identification state Standby state Transfer state Sending-data state Receive-data state Programming state Disconnect state 3.4.1 Card identification mode The host enters the ...

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SMSxxxDF application specific command, therefore APP_CMD (CMD55) shall always precede ACMD41. The RCA to be used for CMD55 in idle state shall be the card’s default RCA = 0x0000. After the host issues a reset command (CMD0) to reset the ...

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Secure digital memory card interface Figure 11. SD memory card state diagram (card identification mode) SPI operation CMD0 + mode CS asserted ('0') No response (invalid command), must be a MultiMediaCard Start MultiMediaCard initialization process starting at CMD1 Card identification ...

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SMSxxxDF CMD7 is used to select one card and switch it to the transfer state. Only one card can be in transfer state at a given time previously selected card is still in transfer state when the host ...

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Secure digital memory card interface Transfer command will be accepted. The DAT0 line will remain Low as long as the card is busy and in the programming stat. Parameter Set commands (CMD16, CMD32, CMD33) are not allowed while the card ...

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SMSxxxDF 3.5 Commands Four types of commands are used to control the SD memory card: 1. Broadcast commands (bc), no response: the broadcast feature is available only if all the CMD lines are interconnected at the level of the host. ...

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Secure digital memory card interface 2. R1b is identical to R1 with an optional busy signal transmitted on the data line. The card may become busy after receiving these commands, depending on the state it was in prior to receiving ...

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SMSxxxDF Table 12. Response R1 Bit position 47 Width (bits) 1 Value ‘0’ Description Start bit Table 13. Response R2 Bit position 135 Width (bits) 1 Value ‘0’ Description Start bit Table 14. Response R3 Bit position 47 Width (bits) ...

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SD memory card hardware interface 4 SD memory card hardware interface 4.1 SD memory card bus circuitry Figure 13 shows the internal bus circuitry required for the SD memory card. The SD memory card may also feature two additional contacts, ...

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SMSxxxDF 4.2 Power-up The power-up time is defined as the voltage rising time from application parameters such as the maximum number of SD cards, the bus length and the characteristic of the power supply unit. ...

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SD memory card hardware interface 4.3 Hot insertion/removal To guarantee a reliable initialization during hot insertion, some measures must be taken on by the host. For example, a special hot-insertion capable card connector may be used to guarantee the sequence ...

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SMSxxxDF Table 17. Bus operating conditions Symbol Peak voltage on all lines Input leakage current Output leakage current V Supply voltage DD Supply voltage specified in OCR register Supply voltage differentials SS1 SS2 Power-up time R , ...

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SD memory card hardware interface Figure 16. Data input/output timings referenced to clock (default) Input Output Table 19. Bus timings (default) Symbol Alt t f Clock frequency data transfer mode KLKL PP Clock frequency identification mode f (the low frequency ...

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SMSxxxDF Figure 17. Data input/output timings referenced to clock (high-speed mode) Input Output Table 20. Bus timings (high speed) Symbol Alt t f Clock frequency data transfer mode KLKL Clock low time KLKH Clock ...

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Card registers 5 Card registers Six registers are defined in the card interface: OCR, CID, CSD, RCA, DSR and SCR. See Table 21 for a description. The registers are accessed by using the corresponding commands. The OCR, CID, CSD and ...

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SMSxxxDF Table 22. OCR register definition OCR bit position 0 24- reserved reserved reserved reserved reserved ...

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Card registers 5.2 CID register The card identification (CID) register contains the card identification information used during the card identification phase. Each flash memory card should have a unique identification number. The structure of the CID register is defined in ...

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SMSxxxDF Table 24. CSD fields compatible with CSD structure card specification V2.11 Name CSD structure Reserved Data read access-time-1 Data read access-time-2 in CLK cycles (NSAC*100) Max. data transfer rate Card command classes Max. read data block ...

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... This value is reserved, the CMD7 command uses it to set all the cards to the standby state. 5.5 DSR register (optional) The 16-bit driver stage register is not used in Numonyx cards. 5.6 SCR register The SD card configuration register (SCR configuration register. The SCR provides information on the special features that are configured in the SD memory card ...

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SMSxxxDF 6 Timings The symbols listed in The difference between P-bits and Z-bits is that P-bits are actively driven to High by the card or the host output driver whereas Z-bits are driven to High and kept High by the ...

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Timings Figure 18. Identification sequence Host command S T CONTENT CMD 6.1.2 Card relative address timings The SD memory card timings for CMD3 (SEND_RELATIVE_ADDR) are given in The minimum delay between the host command and the card response is N ...

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SMSxxxDF 6.1.5 Last host command, next host command timings The host can send a new command N shown in Figure 22. Figure 22. Command sequence (all modes) Host command CMD S T CONTENT 6.2 Data read 6.2.1 Single block read ...

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Timings Figure 24. Multiple Block Read command Host command CMD S T CONTENT CRC E Z DAT **** Figure 25. STOP_TRANSMISSION command (CMD12, data transfer mode) Host command CMD S ...

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SMSxxxDF Figure 26. Block Write command Host N CR command CMD DAT0 DAT1-DAT3 ...

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Timings where the STOP_TRANSMISSION command is implemented: the end bit of the STOP_TRANSMISSION command from the host is followed, on the data line, by one more data bit, then an end bit and two Z-bits. The two Z-bits, which correspond ...

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SMSxxxDF Figure 31. STOP_TRANSMISSION received after last data block with card idle Host command N CR CMD S T CONTENT CRC DAT 6.4.1 Erase, set ...

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Serial peripheral interface (SPI) mode 7 Serial peripheral interface (SPI) mode The SPI mode is a secondary communication protocol, which is available in flash memory- based SD memory cards. The SD memory card SPI implementation uses a subset of the ...

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SMSxxxDF Figure 32. SD memory card system SPI mode bus topology 7.2 SPI bus protocol Whereas the SD channel is based on command and data bit streams initiated by a start bit and terminated by a stop bit, the SPI ...

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Serial peripheral interface (SPI) mode 7.2.2 Bus transfer protection On entering the SPI mode the card defaults to the non-protected mode where there is no CRC (Cyclic Redundancy Check). So systems using reliable data links are not obliged to have ...

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SMSxxxDF Figure 35. Read data error from host to card Data in Command Data out 7.2.4 Data write Single and multiple block write operations are supported in SPI mode. Upon reception of a valid write command, the card sends a ...

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Serial peripheral interface (SPI) mode 7.2.6 Read CID/CSD registers In SPI mode the CID and CSD registers use a block read operation. When a Read command is issued, the card returns a response message followed by a 16-byte data block ...

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SMSxxxDF The commands supported in the SPI mode are described in detail in is required in the command, the value of the field should be set to '0'. Reserved commands are reserved in both the MultiMediaCard and SPI modes. The ...

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Serial peripheral interface (SPI) mode 7.4 Responses There are several types of response tokens the SD mode, all are transmitted MSB first. 7.4.1 R1 format The card sends this response token after every command except for the SEND_STATUS ...

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SMSxxxDF 7.6 SPI bus timings Figure 39 illustrates the basic command/response transaction in SPI mode (that is, when the card is ready). Figure 40 describes a command/ response transaction when the card is busy (R1b response format). For timings, refer ...

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Serial peripheral interface (SPI) mode Figure 39. Host command to card response - card is busy ...

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SMSxxxDF Figure 42. STOP_TRANSMISSION between blocks during multiple block read Read Data in ...

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Serial peripheral interface (SPI) mode Figure 45. Single block write operation Data in X ...

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... SMSxxxDF 8 Package mechanical data To meet environmental requirements, Numonyx offers these devices in ECOPACK packages. ECOPACK packages are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...

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Package mechanical data Table 32. MicroSD package mechanical data Symbol Min A 10.90 A1 9.60 A2 – A3 7.60 A4 – A5 0.75 A8 0.60 B 14.90 B1 6.30 B2 1.64 B3 1.30 B4 0.42 B5 2.80 B7 0.20 B8 ...

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... Other digits may be added to the ordering code for preprogrammed parts or other options. Devices are shipped from the factory with the memory content bits erased to ’1’. For further information on any aspect of the device, please contact the nearest Numonyx sales office. Ordering information ...

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Power supply decoupling Appendix A Power supply decoupling The and V SS1 SS2 decoupling capacitors for buffering current peak are used. These capacitors are placed on the bus side corresponding to Figure 48. Power supply decoupling The ...

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SMSxxxDF 10 Revision history Table 34. Document revision history Date 10-Apr-2008 25-Jun-2008 Revision 1 Initial release. Modified: read and write access for sustained multiple block page 1, Table 1: Device Table 3: Power consumption, 2 and title of Table 19: ...

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