SMS512DFA5E NUMONYX, SMS512DFA5E Datasheet - Page 40

• Manufacturer Part Number: SMS512DFA5E
• Description: MICROSD CARD SMS 512MB FLASH MEM
• Manufacturer: NUMONYX

Specifications of SMS512DFA5E

• Memory Size: 512MB
• Memory Type: SD (Secure Digital)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timings
Figure 24. Multiple Block Read command
Figure 25. STOP_TRANSMISSION command (CMD12, data transfer mode)
6.3
6.3.1
40/60
CMD
DAT
CMD
S T
Z
DAT
Z Z
CONTENT
Data write
Single block write
The host selects one card for the data write operation by issuing CMD7. The host sets the
valid block length for block oriented data transfer by issuing CMD16.
timings of a basic bus write operation. The sequence starts with a Single Block Write
command (CMD24) which determines (in the argument field) the start address. The card
responds on the CMD line.
Data transfer from the host starts N
CRC check bits are appended to the data sent by the host to allow the card to check for
transmission errors. The card returns the CRC check result as a CRC status token on the
DAT0 line. If a transmission error occurred, the card returns a negative CRC status ('101'). If
the transmission completed successfully, the card returns a positive CRC status ('010') and
starts programming the data.
If an error occurred while programming the flash memory, the card ignores all further data
blocks. In this case the card will not send any CRC response and so, there will be no CRC
start bit on the bus and the three CRC status bits will read ('111').
Note that the CRC response is always output two clock cycles after the data.
If the card does not have any data receive buffer available, it indicates this condition by
pulling the DAT0 data line to Low. It will stop pulling DAT0 to Low as soon as at least one
data receive buffer for the defined data transfer block length becomes available. The level of
DAT0 does not give any information about the data write status. The host can obtain this
information by issuing a CMD13 (SEND_STATUS) to the card.
Host command
S
D
****
D D
T
Z
Host command
CONTENT
Z Z Z Z Z P
* * * * * * * * D
CRC E Z
cycles
Z P
N
CRC
N
CR
AC
* P S T
cycles
*******
E
D D E
Z
N
Z
CR
P S
WR
P
Z
CONTENT
cycles
Response
* * * P S
Z
clock cycles after the card response is received.
CONTENT
* * * * * * * * * * * * * * * * * * * *
Read data
CRC E
T
CRC E P
Z Z P P P P P P P P P
CONTENT
Response
N
*******
AC
cycles
CRC E
Figure 26
P
S D D
Read data
shows the
P P P P
SMSxxxDF
D D D
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