20-101-0303 Rabbit Semiconductor, 20-101-0303 Datasheet - Page 48

• Manufacturer Part Number: 20-101-0303
• Description: SMARTSCREEN OP7100 W/TOUCHSCREEN
• Manufacturer: Rabbit Semiconductor

Specifications of 20-101-0303

• Display Type: STN - Super-Twisted Nematic
• Viewing Area: 121.00mm L x 91.00mm W
• Backlight: CCFL - White
• Dot Pitch: 0.36mm x 0.36mm
• Dot Pixels: 320 x 240 (QVGA)
• Interface: Serial
• Product: Prototyping Accessories
• Processor Type: Z180
• Sram: 128 KB
• Flash: 512 KB
• Number Of I/os: 16
• Backup Battery: 3 V Lithium Coin Type
• Operating Voltage: 10 V to 30 V
• Power Consumption: 4.5 W
• Interface Type: Ethernet
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Display Mode: -
• Dot Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 20-101-0303; 20-101-303; 20-101-303; 316-1175

RE (Receiver Enable)
This bit controls the receiver: 1 ⇒ enabled, 0 ⇒ disabled. When this bit is
cleared, the processor aborts the operation in progress, but does not disturb
RDRF or the error flags.
MPE (Multiprocessor Enable)
This bit (1 ⇒ enabled, 0 ⇒ disabled) controls multiprocessor communica-
tion mode which uses an extra bit for selective communication when a
number of processors share a common serial bus. This bit has effect only
when MP in Control Register B is set to 1. When this bit is 1, only bytes
with the MP bit on will be detected. Others are ignored. If this bit is 0, all
bytes received are processed. Ignored bytes do not affect the error flags or
RDRF.
ASCI Control Register B
Control Register B configures the multiprocessor mode, parity, and baud
rate for each channel.
SS (Source/Speed Select)
Coupled with the prescaler (
the source (internal or external clock) and the baud rate divider, as shown
in Table 3-4.
48 Hardware
CNTLB0
MPBT
R / W
7
(02H) and
R / W
MP
*
6
SS2
0
0
0
0
1
1
1
1
May not exceed system clock ÷ 40
Table 3-4. Baud Rate Divide Ratios
CNTLB1
/CTS
R / W
PS
for Source/Speed Select Bits
5
SS1
0
0
1
1
0
0
1
1
PS
(03H)
PEO
R / W
) and the divide ratio (
4
SS0
0
1
0
1
0
1
0
1
R / W
DR
3
external clock*
Divide Ratio
SS2
R / W
2
÷ 16
÷ 32
÷ 64
÷ 1
÷ 2
÷ 4
÷ 8
DR
SS1
R / W
), the
1
SS
SS0
R / W
bits select
0
OP7100