GLK12232-25-SM-V Matrix Orbital, GLK12232-25-SM-V Datasheet - Page 19

• Manufacturer Part Number: GLK12232-25-SM-V
• Description: LCD GRAPHIC DISPL 122X32 WHT BLU
• Manufacturer: Matrix Orbital

Specifications of GLK12232-25-SM-V

• Display Type: LCD - Color
• Display Mode: Transmissive
• Viewing Area: 60.20mm L x 18.00mm W
• Backlight: LED - White
• Dot Size: 0.40mm W x 0.40mm H
• Dot Pitch: 0.44mm x 0.44mm
• Dot Pixels: 122 x 32
• Interface: I²C, RS232, TTL
• Pixel Density: 32 x 122
• Module Size (w X H X T): 65.8 mm x 27 mm x 9.85 mm
• Backlighting: Blue
• Background Color: White
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.1.1 I
able on a single I
that pull up resistors, with a nominal value of 1K to 10K, are placed on the SCL and SDA communication
lines coming from pins two and three of the Data / Power Connector respectively. Data responses by the
module are automatically output via RS232, in case the host will be querying the module, it is necessary
for the host to inform the module that its responses are to be output via I
command 254 /160 / 0 to turn off auto transmission of data in RS232. This will keep the data in the buffer
until the master clocks a read of the slave. The I
units. The GLK12232-25-SM uses 8-bit addressing, with the 8th or Least Significant Bit (LSB) bit desig-
nated as the read/write bit, a 0 designates a write address and a 1 designates a read address. The default
read address of the display module will be 0x51, whereas the write address is 0x50 by default. This address
may be changed by using cmd 254 / 51 / <address>. The GLK12232-25-SM should only be sent addresses
that are even (LSB is 0). When the I
(0101 0000) , since the LSB has to be 0 for an I
GLK12232-25-SM, the effective address is $51 (0101 0001), since the LSB has to be 1 for an I
read.
describe this Phillips I
addressed. When writing to the display module, the display will respond with a ACK when the write has
successfully been completed. However if the buffer has been filled, or the module is too busy processing
data it will respond with a NAK. When performing a multiple byte read within one I
byte read from the slave should be followed by an ACK to indicate that the master still needs data, and a
NAK to indicate that the transmission is over.
considerations when writing I
sent (only needs to be sent once, so this can be done somewhere in init): 254 / 160 / 0 this command puts
the reply data in the I
output buffer, query commands that reply with more than 16 bytes cannot be read (eg cmd Get FileSystem
Directory)
4.1.2 I
sequence. To begin a transaction the data line, SDA, must toggle from high to low while the clock line, SCL,
Matrix Orbital
The GLK12232-25-SM is capable of communicating at 100 KHz in I
If we take a standard Phillips 7 bit address of $45 (100 0101), Matrix Orbital’s GLK12232-25-SM would
The unit does not respond to general call address ($00).
When communicating in I
The GLK12232-25-SM has some speed limitations, especially when run in I
* to be able to read the replies of query commands (eg. cmds 54, 55) the following command must be
* 3ms delay between the read commands
* 625us delay in between data bytes within a transaction is necessary
* 375us between transactions is necessary
The typical I
NOTE These delays are consrevative, and may be decreased based on performance
2
2
C Communication Summary
C Transaction Example
2
2
C transaction contains four parts: the start sequence, addressing, information, and stop
C communication line. However, in order to communicate via I
2
2
C output buffer instead of the RS232 output buffer. Please note that due to a 16 byte
C address as $8A (1000 1010). The read address would be $8B (1000 1011).
2
2
C code:
C the GLK12232-25-SM will send an ACK on the 9th clock cycle when
2
C master wishes to write to the display, the effective address is $50
GLK12232-25-SM
2
2
C data lines operate at 5V normally or 3.3V for -1U style
C master write. When the I
2
2
C mode, with 127 units address-
C. This can be done by sending
2
C master wishes to read the
2
C mode. Here are some
2
C you must first ensure
2
C transaction, each
2
C master
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