AC164335 Microchip Technology, AC164335 Datasheet - Page 79
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AC164335
Manufacturer Part Number
AC164335
Description
MODULE SKT FOR 10X10 PM3 44TQFP
Manufacturer
Microchip Technology
Datasheet
1.AC164335.pdf
(286 pages)
Specifications of AC164335
Module/board Type
Socket Module - TQFP
Product
Microcontroller Accessories
Lead Free Status / RoHS Status
Not applicable / Not applicable
For Use With/related Products
MPLAB® PM3
For Use With
DV007003 - PROGRAMMER UNIVERSAL PROMATE II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not applicable / Not applicable
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6.0
All of the device pins (except V
OSC1/CLKI) are shared between the peripherals and
the parallel I/O ports.
All I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
6.1
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
All port pins have three registers directly associated
with the operation of the port pin. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
FIGURE 6-1:
© 2006 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
I/O PORTS
Parallel I/O (PIO) Ports
Data Bus
WR TRIS
WR LAT +
WR Port
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
Read Port
Peripheral Output Enable
Peripheral Module Enable
Peripheral Output Data
Peripheral Input Data
PIO Module
Peripheral Module
Read TRIS
DD
Read LAT
, V
TRIS Latch
Data Latch
D
D
CK
CK
SS
, MCLR and
Q
Q
Preliminary
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.
Writes to the latch, write the latch (LATx). Reads from
the port (PORTx), read the port pins, and writes to the
port pins, write the latch (LATx).
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs.
A Parallel I/O (PIO) port that shares a pin with a periph-
eral is, in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pad cell. Figure 6-1 shows how ports are shared
with other peripherals, and the associated I/O cell (pad)
to which they are connected. Table 6-1 and Table 6-2
show the register formats for the shared ports, PORTA
through PORTF, for the dsPIC30F1010/2020 and
PORTA through PORTG for the dsPIC30F2023 device,
respectively.
dsPIC30F1010/202X
0
0
1
1
Output Data
Output Enable
Output Multiplexers
Input Data
I/O Cell
I/O Pad
DS70178C-page 77
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