EVAL-ADG2128EB Analog Devices Inc, EVAL-ADG2128EB Datasheet - Page 8

• Manufacturer Part Number: EVAL-ADG2128EB
• Description: BOARD EVAL FOR ADG2128
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADG2128EB

• Main Purpose: Interface, Crosspoint Switch/Multiplexer
• Embedded: No
• Utilized Ic / Part: ADG2128
• Primary Attributes: 8 x 12 Analog Multiplexer, 8 ~ 12V or +/- 5V
• Secondary Attributes: Graphic User Interface
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADG2128
Parameter
t
t
t
t
1
2
3
TIMING DIAGRAM
11
11A
12
SP
Guaranteed by initial characterization. All values measured with input filtering enabled. C
0.3 V
High speed I
A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
DD
and 0.7 V
SDA
SCL
1
2
C is available only in -HS models.
S = START CONDITION
P = STOP CONDITION
DD
Conditions
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Fast mode
High speed mode
P
C
C
C
.
C
C
C
B
B
B
B
B
B
t
= 100 pF maximum
= 100 pF maximum
= 400 pF maximum
7
= 400 pF maximum
= 100 pF maximum
= 400 pF maximum
S
t
6
t
2
2
2
2
2
t
11
t
4
ADG2108 Limit at T
Min
20 + 0.1 C
10
20
20 + 0.1 C
10
20
20 + 0.1 C
10
20
0
0
Figure 2. Timing Diagram for 2-Wire Serial Interface
B
B
B
B
B
B
t
1
t
12
Max
1000
300
40
80
1000
300
80
160
300
300
40
80
50
10
Rev. A | Page 8 of 28
t
3
MIN
, T
MAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
B
refers to capacitive load on the bus line; t
S
Description
t
t
t
Pulse width of suppressed spike
RCL
RCL1
FCL
t
5
t
10
, fall time of SCL signal
, rise time of SCL signal
condition and after an acknowledge bit
, rise time of SCL signal after a repeated start
t
6
R
and t
t
8
F
are measured between
P
t
9