AD1836AZ-DBRD Analog Devices Inc, AD1836AZ-DBRD Datasheet - Page 18

• Manufacturer Part Number: AD1836AZ-DBRD
• Description: BOARD EVAL FOR AD1836A
• Manufacturer: Analog Devices Inc

Specifications of AD1836AZ-DBRD

• Main Purpose: Audio, CODEC
• Embedded: No
• Utilized Ic / Part: AD1836A
• Primary Attributes: 3 Stereo DACs -95 dB THD + N, 108 dB SNR, 2 Stereo ADCs -92 dB THD + N, 105 dB SNR
• Secondary Attributes: Accepts 16/18/20/24-bit Data, SPI Interface, Supports 48 or 96 kHz Sample Rate
• Silicon Manufacturer: Analog Devices
• Application Sub Type: Codec
• Kit Application Type: Audio / Video / TV
• Silicon Core Number: AD1836A
• Kit Contents: Board
• Tool / Board Applications: A/V-Audio Only
• Development Tool Type: Hardware - Daughter Card
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD1836A
Table 11. Pin Function Changes in AUX Mode
Pin Name (I
ASDATA1(O)
ASDATA2(O)/DAUXDATA(O)
DSDATA1(I)
DSDATA2(I)/AAUXDATA(I)
DSDATA3(I)/AAUXDATA2(I)
ALRCLK(O)
ABCLK(O)
DLRCLK(I)/AUXLRCLK(I/O)
DBCLK(I)/AUXBCLK(I/O)
FROM SHARC
FROM EXT A/D
FROM EXT A/D
DLRCLK/AUXLRCLK
DBCLK/AUXBCLK
2
DSDATA3/AUXDATA2
S/AUX Mode)
DSDATA2/AUXDATA1
DSDATA1
MASTER/SLAVE MODE,
FROM ADC SPI PORT
TIMING GEN
LRCLK BCLK
MCLK
I
2
I
I
I
I
I
I
LRCLK for Internal ADC1, ADC2
BCLK for Internal ADC1, ADC2
LRCLK In/Out Internal DACs
BCLK In/Out Internal DACs
2
2
2
2
2
S
2
S Data Out, Internal ADC1
S Data Out, Internal ADC2
S Data In, Internal DAC1
S Data In, Internal DAC2
S Data In, Internal DAC3
S Mode
Figure 12. Extended TDM Mode (Internal Flow Diagram)
DSDATA1
DSDATA2
DSDATA3
LRCLK
BCLK
AUXBCLK
AUXLRCLK
AUXDATA2
AUXDATA1
Rev. 0 | Page 18 of 24
DECODE
ADC
I
INDICATES MUX POSITION FOR AUX-TDM MODE
2
AUX Mode
TDM Data Out, to SHARC
AUX—I
TDM Data In, from SHARC
AUX—I
AUX—I
TDM Frame Sync Out, to SHARC
TDM BCKL Out, to SHARC
AUX LRCLK In/Out, Driven by External IRCLK from ADC (in slave mode).
In master mode, driven by internal MCLK/512.
AUX BCLK In/Out, Driven by External BCLK from ADC (in slave mode).
In master mode, driven by internal MCLK/8.
S
MUX
MUX
2
2
2
4 ADC
S Data Out (to External DAC)
S Data In 1 (to External ADC)
S Data In 2 (to External ADC)
SYNC SIGNAL DERIVED FROM AUXLRCLK USED TO
RESET INTERNAL ADC COUNTER
SYNC
S
AUXLRCLK
SPORT
DAC
AUXDATA
ASDATA1
SPORT
I
2
S FORMATTER
AUXBCLK
CHANNELS
ASDATA1
6 MAIN
ABCLK
LRCLK
MUX
2 AUX
CHANNELS
6-CH
DAC
DATA TO SHARC
ALRCLK
ABCLK
ASDATA1
ASDATA2/DAUXDATA
DATA TO EXT DAC
BCLK AND LRCLK FOR
EXT DAC COMES FROM
ADC BCLK, LRCLK.
MUST BE IN I
2
S MODE.