SI5338-EVB Silicon Laboratories Inc, SI5338-EVB Datasheet
SI5338-EVB
Specifications of SI5338-EVB
Related parts for SI5338-EVB
SI5338-EVB Summary of contents
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... IC is capable of replacing up to four different frequency crystal oscillators or operating as a frequency translator. Using its patented MultiSynth™ technology, the Si5338 allows generation of four independent clocks with 0 ppm precision. Each output clock is independently configurable to support various signal formats and supply voltages. The Si5338 provides low-jitter frequency synthesis in a space-saving QFN package ...
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... Si5338 Functional Block Diagram Osc noclk P1DIV_IN IN1 IN2 ÷P1 IN3 P2DIV_IN IN4 ÷P2 IN5 noclk IN6 Control & Memory OEB/PINC/FINC I2C_LSB/PDEC/FDEC NVM Control SCL (OTP) SDA INTR 2 VDD Synthesis Stage 1 (PLL) ref Loop Phase VCO Filter Frequency Detector fb MultiSynth ÷N RAM Rev ...
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... Configuring the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.8. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9. Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10. Features of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4. Applications of the Si5338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.1. Free-Running Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2. Synchronous Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3. Configurable Buffer and Level Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 ...
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... Si5338 1. Electrical Specifications Table 1. Recommended Operating Conditions (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol Ambient Temperature T A Core Supply Voltage V DD Output Buffer Supply V DDOn Voltage Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. ...
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... DDOx 1,2 CMOS, 200 MHz 3.3 V VDD0 1,2 CMOS, 200 MHz 2.5 V 1,2 CMOS, 200 MHz 1.8 V HSTL, 350 MHz Test Condition Value Still Air 37 Still Air 25 Rev. 1.0 Si5338 Min Typ Max Unit — — — — — — — ...
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... Si5338 Table 5. Performance Characteristics (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol PLL Acquisition Time PLL Tracking Range PLL Loop Bandwidth MultiSynth Frequency Synthesis Resolution CLKIN Loss of Signal Detect Time CLKIN Loss of Signal Release Time PLL Loss of Lock Detect Time ...
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... Pin control UPDATE MultiSynth output >18 MHz 2,3 f Pin control UPDATE MultiSynth output <18 MHz Number of periods of MultiSynth output frequency SS MultiSynth Output < ~Fvco/8 DEV SS MultiSynth Output < ~Fvco/8 DEV Rev. 1.0 Si5338 Min Typ Max Unit — Periods 1 — See ppm 2 Note 5 — ...
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... Si5338 Table 6. Input and Output Clock Characteristics (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol Input Clock (AC Coupled Differential Input Clocks on Pins IN1/2, IN5/6) Frequency f IN Differential Voltage V PP Swing Rise/Fall Time Duty Cycle DC 6 Input Impedance R IN Input Capacitance ...
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... SSTL-3 41 VDDOx = 2.97 to 3.63 V — 0.5xVDDO+0.4 1 SSTL-2 VDDOx = 2.25 to 2.75 V — 0.5xVDDO+0.3 SSTL-18 4 VDDOx = 1.71 to 1.98 V — 0.5xVDDO+0.3 VDDO = 1.4 to 1.6 V — 45 Rev. 1.0 Si5338 Typ Max Units 0.375 0.400 V 0.725 0. — 450 ps — — 200 MHz — 350 MHz ...
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... Si5338 Table 7. Control Pins (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Input Control Pins (IN3, IN4) Input Voltage Low Input Voltage High Input Capacitance Input Resistance Output Control Pins (INTR) Output Voltage Low Rise/Fall Time 20–80% Table 8. Crystal Specifications for MHz ...
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... Load Capacitance (on-chip differential) Crystal Output Capacitance Equivalent Series Resistance Crystal Max Drive Level Symbol Min Typ f 19 XTAL ESR d 100 L Symbol Min Typ f 26 XTAL ESR d 100 L Rev. 1.0 Si5338 Max Unit 26 MHz 100 µW Max Unit 30 MHz 75 µW 11 ...
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... Si5338 1,2,3 Table 12. Jitter Specifications (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol GbE Random Jitter J 4 (12 kHz–20 MHz) GbE Random Jitter R (1.875–20 MHz) OC-12 Random Jitter J OC12 (12 kHz–5 MHz) PCI Express 1.1 Common Clocked PCI Express 2.1 Common Clocked PCI Express 2 ...
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... D J Output MultiSynth operated in integer 7 mode Output MultiSynth operated in fractional 7 mode +14xR Output MultiSynth operated in integer 7 mode 12 rising edges. Rev. 1.0 Si5338 Min Typ Max Unit — 0.7 1.5 ps RMS — pk-pk — pk-pk — pk-pk — pk-pk ...
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... Si5338 Table 13. Typical Phase Noise Performance Offset Frequency 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 2 Table 14 Specifications (SCL,SDA) Parameter Symbol Test Condition LOW Level V ILI2C Input Voltage HIGH Level V IHI2C Input Voltage Hysteresis of V HYS Schmitt Trigger Inputs 2 LOW Level Out- ...
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... INTR CLK3A 19 9 SDA x CLK3B 12 SCL 4 I2C_LSB PAD 23 23 PAD Rev. 1.0 Si5338 SD/HD/3G-SDI Video/Audio SD/HD/3G SDI OUT Video SDI Processor Serializer 100 MHz 100 74.25 MHz, 74.25/1.001 MHz 148.5 MHz, 148.5/1.001 MHz Audio Out Audio IN3 Processor Storage Area ...
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... ClockBuilder Desktop software, which can operate stand alone or in conjunction with the Si5338 EVB. When the software is connected to an Si5338 EVB it will control both the supply voltages to the Si5338 as well as the entire clock path within the Si5338. Clockbuilder Desktop can also measure the current delivered by the EVB regulators to each supply voltage of the Si5338 ...
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... Si5338. IN1 XTAL noclk IN2 Figure 4. Connecting an XTAL to the Si5338 Refer to “AN360: Crystal Selection Guide for Si533x/5x Devices” for information on the crystal selection. 3.2.1. Loss-of-Signal (LOS) Alarm Detectors There are two LOS detectors: LOS_CLKIN and LOS_FDBK ...
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... Si5338 Synthesis of the output clocks is performed in two stages, as shown in Figure 5. The first stage consists of a high-frequency analog phase-locked loop (PLL) that multiplies the input stage to a frequency within the range of 2.2 to 2.84 GHz. Multiplication of the input frequency is accomplished using a proprietary and ...
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... V as needed for the possible output formats. Additionally, the outputs can be configured to stop high, low, or tri-state when the PLL has lost lock. If the Si5338 is used in a zero delay mode, the output that is fed back must be set for always on, which will override any output disable signal ...
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... Si5338C- A00100-GM). Consult your local sales representative for more details on ordering a custom Si5338. 3.5.2. Creating a New Configuration for RAM Any Si5338 device can be configured by writing to 2 registers in RAM through the I C interface. A non- factory programmed device must be configured in this manner ...
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... Copy FCAL values to active registers Set PLL to use FCAL values Set FCAL_OVRD_EN = 1; reg49[7] Enable Outputs Set OEB_ALL = 0; reg230[4] 2 Figure Programming Procedure Rev. 1.0 NO YES NO YES Copy registers as follows: 237[1:0] to 47[1:0] 236[7:0] to 46[7:0] 235[7:0] to 45[7:0] Set 47[7:2] = 000101b Si5338 21 ...
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... An alternative to ordering an Si5338 with a custom NVM configuration is to use the field programming kit (Si5338/56-PROG-EVB) to write directly to the NVM of a “blank” Si5338. Since NVM is an OTP memory, it can only be written once. The default configuration can be reconfigured by writing to RAM through the I (see “3.5.2. Creating a New Configuration for RAM”). ...
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... Control (OTP Enabled OEB 1 = Disabled Figure 12. Output Enable Pin (Si5338K/L/M) 3.7.2. Enabling Outputs through the I Output enable can be controlled through the I interface. As shown in Figure 13, register 230[3:0] allows control of each individual output driver. Register 230[4] controls all drivers at once. When register 230[4] is set to disable all outputs, the individual output enables will have no effect ...
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... When testing for output driver current with LVPECL the same layout pads can be used to implement the LVPECL bias resistor of 130 (2.5 V VDDx) or 200 (3.3 V VDDx). See the schematic in the Si5338-EVB with Si5338-EVB data sheet and AN408 for additional information. 150 200 250 Output Frequency (MHz) Rev ...
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... Reset Options There are two types of resets on the Si5338, POR and soft reset. A POR reset automatically occurs whenever the supply voltage on the VDD is applied. The soft reset is forced by writing 0x02 to register 246. This bit is not self-clearing, and thus it may read back ...
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... IN5/ IN6) to implement an external feedback path which nullifies the delay between the reference input and the output clocks. Figure 15 shows the Si5338 in a typical zero-delay configuration generally recommended that Clk3 be LVDS and that the feedback input be pins 5 and 6 ...
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... Relative Frequency Figure 16. Configurable Spread Spectrum 4. Applications of the Si5338 Because of its flexible architecture, the Si5338 can be configured to serve several functions in the timing path. The following +/- 5% applications. 4.1. Free-Running Clock Generator Using the internal oscillator (Osc) and an inexpensive external crystal (XTAL), the Si5338 can be configured ...
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... MHz), WAN/LAN applications (e.g. 155.52 MHz to 156.25 MHz), and Forward Error Correction (FEC) applications (e.g., 156.25 MHz to 161.1328125 MHz). Using the input reference selectors, the Si5338 can select from one of four inputs (IN1/IN2, IN3, IN4, and IN5/IN6). Figure 18 shows the Si5338 configured as ...
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... SDA 2 Figure 21 and Control Signals The 7-bit device (slave) address of the Si5338 consists of a 6-bit fixed address plus a user-selectable LSB bit as shown in Figure 22. The LSB bit is selectable using the optional I2C_LSB pin which is available as an ordering option for applications that require more than one ...
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... However, for customers interested in using the Si5338 in operating modes beyond the capabilities available with ClockBuilder™, refer to “AN411: Configuring the Si5338” for a detailed description of the Si5338 registers and their usage. Also refer to “AN428: Jump Start: In- System, Flash-Based Programming for Silicon Labs’ ...
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... Table 15. Si5338 Pin Descriptions CLKIN/CLKINB. These pins are used as the main differential clock input or as the XTAL input. See "3.2. Input Stage" on page 17, Figure 3 and Figure 4, for connection details. Clock inputs to these pins must be Multi ac-coupled. Keep the traces from pins 1,2 to the crystal as short as possible and keep other signals and radiating sources away from the crystal ...
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... This pin can have one of the following functions depending on the part number 2 I C_LSB (for Si5338A/B/C and Si5338K/L/M devices only) This is the LSB of the Si5338 I 2 70h (111 0000 address 71h (111 0001). FDBK (for Si5338N/P/Q devices only) Provides a high-impedance feedback input for single-ended clock signals. This input should be dc-coupled as shown in “ ...
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... Table 15. Si5338 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Type 5,6 IN5/IN6 I Multi 7 VDD VDD Supply 8 INTR O Open Drain 9 CLK3B O Multi 10 CLK3A O Multi 11 VDDO3 VDD Supply 12 SCL I LVCMOS 13 CLK2B O Multi 14 CLK2A O Multi Description FDBK/FDBKB. These pins can be used as a differential feedback input in zero delay mode secondary clock input. See section 3.2, Figure 3, for termination details. See " ...
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... Si5338 Table 15. Si5338 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Type 15 VDDO2 VDD Supply 16 VDDO1 VDD Supply 17 CLK1B O 18 CLK1A O 19 SDA I/O LVCMOS 20 VDDO0 VDD Supply 21 CLK0B O 22 CLK0A O 23 RSVD_GND GND 24 VDD VDD Supply GND GND GND PAD 34 Output Clock Supply Voltage ...
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... Device Pinout by Part Number The Si5338 is orderable in three different speed grades: Si5338A/D/G/K/N have a maximum output clock frequency limit of 710 MHz. Si5338B/E/H/L/P have a maximum output clock frequency of 350 MHz. Si5338C/F/J/ M/Q have a maximum output clock frequency of 200 MHz. Devices are also orderable according to the pin control functions available on Pins 3 and 4: ...
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... Si5338 Table 16. Pin Function by Part Number (Continued) Pin # Si5338A: 710 MHz Si5338D: 710 MHz Si5338B: 350 MHz Si5338E: 350 MHz Si5338C: 200 MHz Si5338F: 200 MHz 17 CLK1B 18 CLK1A 19 SDA 20 VDDO0 21 CLK0B 22 CLK0A 23 GND 24 VDD Notes: 1. CLKIN/CLKINB on pins 1 and 2 are differential clock inputs or XTAL inputs. ...
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... Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Table 17. Package Dimensions Min Nom 0.80 0.85 0.00 0.02 0.18 0.25 4.00 BSC. 2.35 2.50 0.50 BSC. 4.00 BSC. 2.35 2.50 0.30 0.40 0.10 0.10 0.08 0.10 0.05 Rev. 1.0 Si5338 Max 0.90 0.05 0.30 2.65 2.65 0.50 37 ...
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... Si5338 10. Recommended PCB Layout Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. Connect the center ground pad to a ground plane with no less than five vias. These 5 vias should have a length of no more than 20 mils to the ground plane ...
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... Line 4 YYWW Si5338 Xxxxxx RTTTTT YYWW Figure 26. Si5338 Top Marking Table 19. Top Marking Explanation Description Base part number Frequency and configuration code. xxxxx = Optional NVM code for custom factory-programmed devices (characters are not included for blank devices). See "12. Ordering Information" on page 40. ...
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... When ordering non Tape & Reel shipment media, contact your sales representative for more information Product Revision A XXXXX = NVM code (optional). For blank devices, order Si5338X-A-GM(R). For custom NVM configurations, a unique 5-digit ordering code will be assigned by the factory. Consult your sales representative for custom NVM configurations. EVB ...
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... Added new Si5338N/P/Q ordering codes Added typical application diagrams Added an application section to highlight the flexibility of the Si5338 in various timing functions Added a configuration section to clarify configuration options Revision 0.5 to 0.55 Editorial changes to section 3.5 “Configuring the Si5338” ...
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... Si5338 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...