SI5338-EVB Silicon Laboratories Inc, SI5338-EVB Datasheet - Page 23
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SI5338-EVB
Manufacturer Part Number
SI5338-EVB
Description
BOARD EVALUATION SI5338
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI5338B-A-GM.pdf
(42 pages)
Specifications of SI5338-EVB
Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
Si5338
Primary Attributes
160 kHz to 700 MHz in LVPECL/LVDS,
Secondary Attributes
USB Based GUI to Program, I2C/SMBus Compatible Interface, 1.8, 2.5, or 3.3 V
For Use With/related Products
Si5330/34/38 Family
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1556
3.7.2. Enabling Outputs through the I
Output enable can be controlled through the I
interface. As shown in Figure 13, register 230[3:0]
allows control of each individual output driver. Register
230[4] controls all drivers at once. When register 230[4]
is set to disable all outputs, the individual output
enables will have no effect. Registers 110[7:6], 114[7:6],
118[7:6], and 112[7:6] control the output disabled state
as tri-state, low, high, or always on. If always on is set,
that output will always be on regardless of any other
register or chip state. In addition, the always on mode
must be selected for an output that is fed back in a Zero
Delay application.
Figure 12. Output Enable Pin (Si5338K/L/M)
Figure 13. Output Enable Control Registers
1 = Disabled
0 = Enabled
118
230
110
114
122
0 = enable
1 = disable
00 = disabled tri-state
01 = disabled low
10 = disabled high
11 = always enabled
CLK0 OEB
CLK1 OEB
CLK2 OEB
CLK3 OEB
7
7
7
7
7
OEB
State
State
State
State
6
6
6
6
6
5
5
5
5
5
OEB
All
4
4
4
4
4
Bits reserved
OEB
Control
3
3
3
3
3
3
Control & Memory
Bits used by other functions
OEB
2
2
2
2
2
2
(OTP)
NVM
OEB
1
1
1
1
1
1
2
RAM
C Interface
OEB
0
0
0
0
0
0
2
Rev. 1.0
C
Si5338
23