DS50PCI402EVK/NOPB National Semiconductor, DS50PCI402EVK/NOPB Datasheet - Page 30

• Manufacturer Part Number: DS50PCI402EVK/NOPB
• Description: BOARD EVALUATION DS50PCI402
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DS50PCI402EVK/NOPB

• Main Purpose: Interface, Transceiver, PCI Express
• Embedded: No
• Utilized Ic / Part: DS50PCI402
• Primary Attributes: 5 Gbps Quad Lane Bidirectional Buffer & Equalizer
• Secondary Attributes: 3.3V LVCMOS Input Tolerant for SMBus Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS50PC1402EVK/NOPB

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Applications Information
GENERAL RECOMMENDATIONS
The DS50PCI402 is a high performance circuit capable of
delivering excellent performance. Careful attention must be
paid to the details associated with high-speed design as well
as providing a clean power supply. Refer to the information
below and the latest version of the LVDS Owner's Manual for
more detailed information on high speed design tips to ad-
dress signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The CML inputs and LPDS outputs have been optimized to
work with interconnects using a controlled differential
The graphic shown above depicts different transmission line
topologies which can be used in various combinations to
achieve the optimal system performance. Impedance discon-
tinuities at the differential via can be minimized or eliminated
by increasing the swell around each hole and providing for a
low inductance return current path. When the via structure is
associated with thick backplane PCB, further optimization
such as back drilling is often used to reduce the deterimential
high frequency effects of stubs on the signal path.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS50PCI402 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
FIGURE 8. Typical Routing Options
30
impedance of 85 - 100Ω. It is preferable to route differential
lines exclusively on one layer of the board, particularly for the
input traces. The use of vias should be avoided if possible. If
vias must be used, they should be used sparingly and must
be placed symmetrically for each side of a given differential
pair. Whenever differential vias are used the layout must also
provide for a low inductance path for the return currents as
well. Route the differential signals away from other signals
and noise sources on the printed circuit board. See AN-1187
for additional information on LLP packages.
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the V
a low inductance supply with distributed capacitance. Sec-
ond, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.01 μF bypass ca-
pacitor should be connected to each V
capacitor is placed as close as possible to the DS50PCI402.
Smaller body size capacitors can help facilitate proper com-
ponent placement. Additionally, three capacitors with capac-
itance in the range of 2.2 μF to 10 μF should be incorporated
in the power supply bypassing design as well. These capac-
itors can be either tantalum or an ultra-low ESR ceramic.
DD
and GND planes create
DD
pin such that the
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