DS50PCI402EVK/NOPB National Semiconductor, DS50PCI402EVK/NOPB Datasheet - Page 6

• Manufacturer Part Number: DS50PCI402EVK/NOPB
• Description: BOARD EVALUATION DS50PCI402
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DS50PCI402EVK/NOPB

• Main Purpose: Interface, Transceiver, PCI Express
• Embedded: No
• Utilized Ic / Part: DS50PCI402
• Primary Attributes: 5 Gbps Quad Lane Bidirectional Buffer & Equalizer
• Secondary Attributes: 3.3V LVCMOS Input Tolerant for SMBus Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS50PC1402EVK/NOPB

www.national.com
Functional Description
The DS50PCI402 is a low power media compensation 4 lane
repeater optimized for PCI Express Gen 1 and Gen 2 media
including lossy FR-4 printed circuit board backplanes and
balanced cables. The DS50PCI402 operates in two modes:
Pin Control Mode (ENSMB = 0) and SMBus Mode (ENSMB
= 1).
Pin Control Mode:
When in pin mode (ENSMB = 0) , the repeater is configurable
with external pins. Equalization and de-emphasis can be se-
lected via pin for each side independently. When de-empha-
sis is asserted VOD is automatically increased per the De-
Emphasis table below for improved performance over lossy
media. The receiver detect pins RXDETA/B provide manual
control for input termination (50Ω or >50KΩ). Rate optimiza-
tion is also pin controllable, with pin selections for 2.5Gbps,
5Gbps, and auto detect. The receiver electrical idle detect
threshold is also programmable via an optional external re-
sistor on the SD_TH pin.
SMBUS Mode:
When in SMBus mode the equalization, de-emphasis, and
termination disable features are all programmable on a indi-
EQ1 EQ0
EQ1 EQ0
F
1
0
F
F
0
F
1
0
0
1
1
F=Float (don't drive pin, each float pin has an internal 50K Ohm resistor to VDD and GND), 1=High, 0=Low
F=Float (don't drive pin, each float pin has an internal 50K Ohm resistor to VDD and GND), 1=High, 0=Low
[1:0]
[1:0]
GST
GST
EQ Setting
EQ Setting
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
[2:0]
[2:0]
BST
BST
000
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
TABLE 1. Equalization Settings with GST=1 for Pins or SMBus Registers
TABLE 2. Equalization Settings with GST=2 for Pins or SMBus Registers
1.25 GHz
1.25 GHz
11.3
12.3
12.8
1.6
2.1
2.6
3.2
4.0
4.9
5.4
5.6
3.8
5.1
6.4
7.6
9.5
0
EQ Gain (dB)
EQ Gain (dB)
2.5 GHz
2.5 GHz
11.6
13.5
16.1
17.5
18.6
19.8
3.2
4.2
5.0
5.9
7.3
7.9
8.5
9.0
7.6
9.9
0
6
vidual lane basis, instead of grouped by sides as in the pin
mode case. Upon assertion of ENSMB the RATE, EQx and
DEMx functions revert to register control immediately. The
EQx and DEMx pins are converted to AD0-AD3 SMBus ad-
dress inputs. The other external control pins remain active
unless their respective registers are written to and the appro-
priate override bit is set, in which case they are ignored until
ENSMB is driven low. On powerup and when ENSMB is driv-
en low all registers are reset to their default state. If PRSNT
is asserted while ENSMB is high, the registers retain their
current state.
Equalization settings accessible via the pin controls were
chosen to meet the needs of most PCIe applications. If addi-
tional fine tuning or adjustment is needed, additional equal-
ization settings can be accessed via the SMBus registers.
Each input has a total of 24 possible equalization settings.
The tables show a typical gain for each gain stage (GST[1:0])
and boost level (BST[2:0]) combination. When using SMBus
mode, the Equalization and De-Emphasis levels are set using
registers.
50" FR4 (6-mil trace) or 10m (24 AWG) PCIe cable
8" FR4 (6-mil trace) or < 1m (28 AWG) PCIe cable
14" FR4 (6-mil trace) or 1m (28 AWG) PCIe cable
20" FR4 (6-mil trace) or 5m (26 AWG) PCIe cable
40" FR4 (6-mil trace) or 9m (24 AWG) PCIe cable
Bypass - Default Setting
Suggested Use
Suggested Use