EVAL-AD5235EBZ Analog Devices Inc, EVAL-AD5235EBZ Datasheet - Page 18

• Manufacturer Part Number: EVAL-AD5235EBZ
• Description: BOARD EVALUATION FOR AD5235
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5235EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: AD5235
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

AD5235
DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes. It can be
used to read the contents of the wiper setting and EEMEM values
using Instruction 10 and Instruction 9, respectively. The remaining
instructions (Instruction 0 to Instruction 8, Instruction 11 to
Instruction 15) are valid for daisy-chaining multiple devices in
simultaneous operations. Daisy-chaining minimizes the number
of port pins required from the controlling IC (see Figure 41). The
SDO pin contains an open-drain N-Ch FET that requires a pull-up
resistor, if this function is used. As shown in Figure 41, users need
to tie the SDO pin of one package to the SDI pin of the next package.
Users may need to increase the clock period because the pull-up
resistor and the capacitive loading at the SDO-to-SDI interface may
require additional time delay between subsequent devices.
When two AD5235s are daisy-chained, 48 bits of data are
required. The first 24 bits (formatted 4-bit command, 4-bit
address, and 16-bit data) go to U2, and the second 24 bits with
the same format go to U1. Keep CS low until all 48 bits are
clocked into their respective serial registers. CS is then pulled
high to complete the operation.
TERMINAL VOLTAGE OPERATING RANGE
The positive V
define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminal A,
Terminal B, and Terminal W that exceed V
the internal forward-biased diodes (see Figure 42).
CONTROLLER
MICRO-
SCLK SS
Figure 42. Maximum Terminal Voltages Set by V
MOSI
Figure 41. Daisy-Chain Configuration Using SDO
DD
and negative V
SDI
CS
AD5235
U1
CLK
SDO
SS
power supplies of the AD5235
V
DD
R
2.2k
P
DD
Ω
or V
SDI
CS
AD5235
SS
DD
U2
V
V
A
W
B
are clamped by
SS
and V
DD
CLK
SDO
SS
Rev. D | Page 18 of 32
The GND pin of the AD5235 is primarily used as a digital
ground reference. To minimize the digital ground bounce,
the AD5235 ground terminal should be joined remotely to
the common ground (see Figure 43). The digital input control
signals to the AD5235 must be referenced to the device ground
pin (GND) and must satisfy the logic level defined in the
Specifications section. An internal level-shift circuit ensures
that the common-mode voltage range of the three terminals
extends from V
Power-Up Sequence
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 42), it
is important to power V
voltage to Terminal A, Terminal B, and Terminal W. Otherwise,
the diode is forward-biased such that V
unintentionally. For example, applying 5 V across Terminal A
and Terminal B prior to V
4.3 V. It is not destructive to the device, but it might affect the
rest of the user’s system. The ideal power-up sequence is GND,
V
powering V
long as they are powered after V
Regardless of the power-up sequence and the ramp rates of the
power supplies, when V
preset activates, which restores the EEMEM values to the RDAC
registers.
Layout and Power Supply Bypassing
It is a good practice to employ compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Bypass supply leads to
the device with 0.01 μF to 0.1 μF disk or chip ceramic capacitors.
Also, apply low ESR, 1 μF to 10 μF tantalum or electrolytic
capacitors at the supplies to minimize any transient disturbance
(see Figure 43).
DD
and V
SS
V
V
A
, digital inputs, and V
DD
SS
, V
SS
10µF
10µF
B
, V
C3
C4
to V
Figure 43. Power Supply Bypassing
W
, and the digital inputs is not important as
+
+
DD
0.1µF
0.1µF
, regardless of the digital input level.
DD
DD
C1
C2
DD
and V
and V
causes the V
DD
SS
SS
A
and V
, V
are powered, the power-on
first before applying any
V
V
DD
SS
B
DD
, and V
AD5235
SS
GND
and V
DD
.
terminal to exhibit
W
SS
. The order of
are powered