CRD8900A-1 Cirrus Logic Inc, CRD8900A-1 Datasheet
CRD8900A-1
Specifications of CRD8900A-1
Related parts for CRD8900A-1
CRD8900A-1 Summary of contents
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... Ethernet circuit that occupies less than 1.5 square inches (10 sq. cm) of board space. ORDERING INFORMATION CS8900A-CQZ CS8900A-IQZ -40° to 85° CS8900A-CQ3Z 0° to 70° C 3.3V CS8900A-IQ3Z -40° to 85° C 3.3V CRD8900A-1 20 MHz XTAL CS8900A ISA Ethernet Controller LED Clock 10BASE-T Control RX Filters & ...
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TABLE OF CONTENTS 1.0 INTRODUCTION ......................................................................................................................8 1.1 General Description ...........................................................................................................8 1.1.1 Direct ISA-Bus Interface .......................................................................................8 1.1.2 Integrated Memory ...............................................................................................8 1.1.3 802.3 Ethernet MAC Engine .................................................................................8 1.1.4 EEPROM Interface ...............................................................................................8 1.1.5 Complete Analog Front End .................................................................................8 1.2 System Applications ..........................................................................................................8 1.2.1 ...
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CS8900A Crystal LAN™ Ethernet Controller 3.4.7.1 Determining EEPROM Size .................................................................24 3.4.7.2 Loading Configuration Data .................................................................24 3.4.8 EEPROM Read-out Completion ......................................................................... 24 3.5 Programming the EEPROM ............................................................................................ 25 3.5.1 EEPROM Commands ........................................................................................ 25 3.5.2 EEPROM Command Execution ......................................................................... 25 3.5.3 Enabling ...
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Interface Selection ............................................................................................36 3.10.4.1 10BASE-T Only .................................................................................36 3.10.4.2 AUI Only ............................................................................................36 3.10.4.3 Auto-Select ........................................................................................36 3.11 10BASE-T Transceiver ..................................................................................................36 3.11.1 10BASE-T Filters ..............................................................................................37 3.11.2 Transmitter .......................................................................................................37 3.11.3 Receiver ...........................................................................................................37 3.11.3.1 Squelch Circuit ...................................................................................37 3.11.3.2 Extended Range ................................................................................38 3.11.4 Link Pulse ...
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CS8900A Crystal LAN™ Ethernet Controller 4.10.2 TxCMD Port ...................................................................................................... 75 4.10.3 TxLength Port ................................................................................................... 76 4.10.4 Interrupt Status Queue Port ............................................................................. 76 4.10.5 PacketPage Pointer Port .................................................................................. 76 4.10.6 PacketPage Data Ports 0 and 1 ....................................................................... 76 4.10.7 I/O Mode ...
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Overview .............................................................................................................94 5.4.2 Configuring the CS8900A for Auto-Switch DMA .................................................94 5.4.3 Auto-Switch DMA Operation ...............................................................................94 5.4.4 DMA Channel Speed vs. Missed Frames ...........................................................95 5.4.5 Exit From DMA ...................................................................................................96 5.4.6 Auto-Switch DMA Example .................................................................................96 5.5 StreamTransfer ...............................................................................................................96 5.5.1 Overview .............................................................................................................96 ...
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CS8900A Crystal LAN™ Ethernet Controller Release Date PP1 NOV 1997 Preliminary Release, revision 1 PP2 DEC 1998 Preliminary Release, revision 2 PP3 MAR 1999 Preliminary Release, revision 3 PP4 APR 2001 Preliminary Release, revision 4 Page 13: INTRQ[0:2] changed to ...
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INTRODUCTION 1.1 General Description The CS8900A is a true single-chip, full-duplex, Ethernet solution, incorporating all of the ana- log and digital circuitry needed for a complete Ethernet circuit. Major functional blocks in- clude: a direct ISA-bus interface; an 802.3 ...
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CS8900A Crystal LAN™ Ethernet Controller Figure 1. Complete Ethernet Motherboard Solution high level of integration allow System Engi- neers to design a complete Ethernet circuit that occupies as little as 1.5 square inches of PCB area (Figure ...
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On-chip LED ports can be used for either optional LEDs programmable out- puts. 1.3 Key Features and Benefits 1.3.1 Very Low Cost The CS8900A is designed to provide the low- est-cost Ethernet solution available for embed- ded ...
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CS8900A Crystal LAN™ Ethernet Controller 20 MHz 97 98 EEPROM XTAL XTAL 93C46 EECS EEDATAIN EEDATAOUT 2 4 CLK EESK ISA Address BUS Decoder 4 7 LA[20:23] CHIPSEL PAL BALE ...
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PIN DESCRIPTION AVSS0 1 ELCS 2 EECS 3 EESK 4 EEDataOut 5 EEDataIn 6 7 CHIPSEL 8 DVSS1 9 DVDD1 10 DVSS1A DMARQ2 11 DMACK2 12 DMARQ1 13 DMACK1 14 DMARQ0 15 DMACK0 16 CSOUT 17 SD15 18 SD14 ...
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CS8900A Crystal LAN™ Ethernet Controller ISA Bus Interface SA[0:19] - System Address Bus, Input PINS 37-48, 50-54, 58-60. Lower 20 bits of the 24-bit System Address Bus used to decode accesses to CS8900A I/O and Memory space, and attached Boot ...
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IOW - I/O Write, Input PIN 62. When IOW is low and a valid address is detected, the CS8900A writes the data on the System Data Bus into the selected 16-bit I/O register. IOW is ignored if REFRESH is low. ...
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CS8900A Crystal LAN™ Ethernet Controller EECS - EEPROM Chip Select, PIN 3. Active-high output used to select the EEPROM. EEDataIn - EEPROM Data In, Input Internal Weak Pullup PIN 6. Serial input used to receive data from the EEPROM. Connects ...
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General Pins XTAL[1:2] - Crystal, Input/Output PINS 97 and 98 MHz crystal should be connected across these pins crystal is not used MHz signal should be connected to XTAL1 and XTAL2 should be left ...
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CS8900A Crystal LAN™ Ethernet Controller 3.0 FUNCTIONAL DESCRIPTION 3.1 Overview During normal operation, the CS8900A per- forms two basic functions: Ethernet packet transmission and reception. Before transmis- sion or reception is possible, the CS8900A must be configured. 3.1.1 Configuration The ...
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Memory space operations, I/O space oper- ations DMA operations using host DMA. Also, the CS8900A provides the capability to switch between Memory or I/O operation and DMA operation by using Auto-Switch DMA and StreamTransfer. The Section 5.2 ...
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CS8900A Crystal LAN™ Ethernet Controller memory. The CS8900A has three pairs of DMA pins that can be connected directly to the three 16-bit DMA channels of the ISA bus. Only one DMA channel is used at a time ...
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Allowing Time for Reset Operation After a reset, the CS8900A goes through a self configuration. This includes calibrating on-chip analog circuitry, and reading EEPROM for va- lidity and configuration. Time required for the reset calibration is typically 10 ms. ...
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CS8900A Crystal LAN™ Ethernet Controller PacketPage Register Register Descriptions Address Contents 0020h 0300h I/O Base Address* 0022h XXXX XXXX Interrupt Number XXXX X100 0024h XXXX XXXX DMA Channel XXXX XX11 0026h 0000h DMA Start of Frame Offset 0028h X000h DMA ...
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Word Address Value FIRST WORD in DATA BLOCK 00h A120h FIRST GROUP of WORDS 01h 2020h 02h 0300h 03h 0003h 04h 0001h SECOND GROUP of WORDS 05h 502Ch 06h E000h 07h 000Fh 08h 0000h 09h 000Dh 0Ah C000h 0Bh 000Fh ...
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CS8900A Crystal LAN™ Ethernet Controller bytes of configuration data are stored in the Reset Configuration Block. 3.4.3.3 Determining the EEPROM Type The LSB of the high byte of the header indi- cates the type of EEPROM attached: sequen- tial or ...
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Bits 8 through 0 of the Group Header specify a 9-bit PacketPage Address. This address de- fines the PacketPage register that will be load- ed with the first word of configuration data from the group. Bits B though 9 of ...
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CS8900A Crystal LAN™ Ethernet Controller initialization is complete (configuration loaded from EEPROM or reset to default configura- tion) the INITD bit is set (Register 16, SelfST, bit 7). 3.5 Programming the EEPROM After initialization, the host can access the EE- ...
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CS8900A, into the EEPROM. If the command is a Write, the data in the EEPROM Data register (PacketPage base + 0042h) fol- lows. If the command is a ...
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CS8900A Crystal LAN™ Ethernet Controller and the Address Mask is FC000h. This config- uration describes a 16-Kbyte (128 Kbit) PROM mapped into host memory from D0000h to D3FFFh. 3.7 Low-Power Modes For power-sensitive applications, CS8900A supports three low-power modes: Hardware ...
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To exit SW Suspend, the host must write to the CS8900A’s assigned I/O space (the Write is only used to wake the CS8900A, the Write itself is ignored). Upon exit, the CS8900A per- forms a complete reset, and then ...
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CS8900A Crystal LAN™ Ethernet Controller 3.8 LED Outputs The CS8900A provides three output pins that can be used to control LEDs or external logic. 3.8.1 LANLED LANLED goes low whenever the CS8900A transmits or receives a frame, or when it ...
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CRC generation and test. Pro- grammable MAC features include automatic retransmission on collision, and padding of transmitted frames. Figure 8 shows how the MAC engine interfac other CS8900A functions. On the ...
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CS8900A Crystal LAN™ Ethernet Controller tire packet has been received, the MAC vali- dates the FCS error is detected, the CRCerror bit (Register 4, RxEvent, Bit C) is set. 3.9.2.3 Enforcing Minimum Frame Size The MAC provides minimum ...
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The collision count is stored in bits B through E of the TxEvent reg- ister (Register 8). If the packet collides 16 times, transmission of that packet is terminat- ed and the 16coll bit (Register 8, TxEvent, Bit ...
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CS8900A Crystal LAN™ Ethernet Controller attempting transmission. The CS8900A sup- ports two schemes for determining when to ini- tiate transmission: Two-Part Deferral, and Simple Deferral. Selection of the deferral scheme is determined by the 2-partDefDis bit (Register 13, LineCTL, Bit ...
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Collision Resolution If a collision is detected while the CS8900A is transmitting, the MAC responds in one of three ways depending on whether normal col- lision (within the first 512 bits of transmission late ...
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CS8900A Crystal LAN™ Ethernet Controller bit times), and k is the smaller 10, where n is the number of retransmission attempts. 3.9.5.9 Modified Backoff The Modified Backoff is described by the equation: 0 ≤ r ≤ 2 ...
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The specifications for the crys- tal are described in Section 7.7 on page 122. The encoded signal is routed to either the 10BASE-T transceiver or AUI, depending on configuration. 3.10.2 Carrier Detection The internal Carrier Detection circuit ...
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CS8900A Crystal LAN™ Ethernet Controller LinkOK (to MAC) RXSQL RX ENDEC TX 3.11.1 10BASE-T Filters The CS8900A’s 10BASE-T transceiver in- cludes integrated low-pass transmit and re- ceive filters, eliminating the need for external filters or a filter/transformer hybrid. On-chip fil- ...
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Extended Range The CS8900A supports an Extended Range feature that reduces the 10BASE-T receive squelch threshold by approximately 6 dB. This allows the CS8900A to operate with 10BASE- ...
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CS8900A Crystal LAN™ Ethernet Controller at least four frames in a row with negative po- larity after the EOF, the receive pair is consid- ered reversed. Any data received before the correction of the reversal is ignored. 3.11.6 Collision Detection ...
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External Clock Oscillator A 20-MHz quartz crystal or CMOS clock input is required by the CS8900A CMOS clock input is used, it should be connected the to XTAL1 pin, with the XTAL2 pin left open. The 40 ...
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CS8900A Crystal LAN™ Ethernet Controller 4.0 PACKETPAGE ARCHITECTURE 4.1 PacketPage Overview The CS8900A architecture is based on a unique, highly-efficient method of accessing internal registers and buffer memory known as PacketPage. PacketPage provides a unified way of controlling the CS8900A ...
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The host simply writes to and reads from these locations and internal buffer memory is dynamically allocated be- tween transmit and receive as needed. This provides more efficient use of buffer memory and better overall ...
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CS8900A Crystal LAN™ Ethernet Controller PacketPage # of Type Address Bytes 0100h 32 Read/Write Configuration & Control Registers 0120h 32 Read-only Status & Event Registers 0140h 4 - Initiate Transmit Registers 0144h 2 Write-only TxCMD (transmit command) 0146h 2 Write-only ...
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Bus Interface Registers 4.3.1 Product Identification Code (Read only, Address: PacketPage base + 0000h) Address 0000h First byte of EISA registration number for registration number for Crystal Semiconductor Crystal Semiconductor The Product Identification Code Register is located in the ...
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CS8900A Crystal LAN™ Ethernet Controller ing bus signals are tied to the following pins: See Section 3.2 on page 18. After reset EEPROM is found by the CS8900A, then the register has the following initial state, which corre- ...
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Reset value is: 0000 0000 0000 0000 4.3.6 DMA Frame Count (Read only, Address: PacketPage base + 0028h) Address 0029h Most significant byte of frame count (most-significant nibble always 0h) The lower 12 bits of the DMA Frame Count register ...
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CS8900A Crystal LAN™ Ethernet Controller The lower three bytes (0030h, 0031h, and 0032h) of the Boot PROM Base Address register are used for the 20-bit Boot PROM base address. The upper three nibbles are reserved. See Section 3.6 on page ...
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Reset value is: XXXX XXXX XXXX XXXX 4.3.12 EEPROM Data (Read/Write, Address: PacketPage base + 0042h) Address 0043h Most significant byte of the EEPROM data. This register contains the word being written to, or read from, the EEPROM. See Section ...
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CS8900A Crystal LAN™ Ethernet Controller 4.4 Status and Control Registers The Status and Control registers are the pri- mary registers used to control and check the status of the CS8900A. They are organized into two groups: Configuration/Control Regis- ters and ...
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The following sections contain more information about these counters. Suffix Type CMD Read/Write Command: Written once per frame to initiate transmit. CFG Read/Write Configuration: Written at setup and used to determine what frames will ...
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CS8900A Crystal LAN™ Ethernet Controller Interrupt Enable Bit Event Bit or Counter (register name) (register name) ExtradataiE (RxCFG) Extradata (RxEvent) RuntiE (RxCFG) Runt (RxEvent) CRCerroriE (RxCFG) CRCerror (RxEvent) RxOKiE (RxCFG) RxOK (RxEvent) 16colliE (TxCFG) 16coll (TxEvent) AnycolliE (TxCFG) “Number-of Tx-collisions” ...
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Control and Configuration Bits Reserved (register contents undefined) Extra RuntiE CRC dataiE erroriE Extra RuntA CRC dataA errorA 16colli E TxPad- Inhibit- Dis CRC RxDe Miss TxCol stiE OvfloiE OvfloiE Reserved (register contents undefined) LoRx 2-part ...
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CS8900A Crystal LAN™ Ethernet Controller Reserved (register contents undefined) Extra Runt CRC data error Hash Table Index (alternate RxEvent meaning if Hashed = 1 and RxOK = 1) Reserved (register contents undefined) 16coll Number-of-Tx-collisions Reserved (register ...
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RegNum The lower six bits describe which register ( 12) is contained in the ISQ. RegContent The upper ten bits contain the register data contents. Reset value is: 0000 0000 0000 0000 4.4.6 Register 3: Receiver ...
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CS8900A Crystal LAN™ Ethernet Controller 4.4.7 Register 4: Receiver Event (RxEvent, Read-only, Address: PacketPage base + 0124h Dribblebits IAHash F E Extradata Runt Alternate meaning if bits 8 and 9 are both set (see Section 5.2.10 on page ...
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Register 5: Receiver Control (RxCTL, Read/Write, Address: PacketPage base +0104h PromiscuousA IAHashA F E ExtradataA RuntA RxCTL has two functions: Bits and E define what types of frames to accept. Bits ...
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CS8900A Crystal LAN™ Ethernet Controller 4.4.9 Register 7: Transmit Configuration (TxCFG, Read/Write, Address: PacketPage base + 0106h SQE erroriE Loss-of-CRSiE F E 16colliE Each bit in TxCFG is an interrupt enable. When set, the interrupt is enabled as ...
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These bits provide an internal address used by the CS8900A to identify this as the Transmitter Event Register. Loss-of-CRS If the CS8900A is transmitting on the AUI and doesn't see Carrier Sense (CRS) at the end of the preamble, ...
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CS8900A Crystal LAN™ Ethernet Controller Bit 7 Bit Start transmission after 5 bytes are in the CS8900A 0 1 Start transmission after 381 bytes are in the CS8900A 1 0 Start transmission after 1021 bytes are in ...
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RxMissiE When set, there is an interrupt if one or more received frames is lost due to slow movement of receive data ...
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CS8900A Crystal LAN™ Ethernet Controller TxUnderrun This bit is set if CS8900A runs out of data before it reaches the end of the frame (called a trans- mit underrun). If TxUnderruniE (Register B, BufCFG, Bit 9) is set, there is ...
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CFG, Bit C) is set, there is an interrupt when TxCOL increments from 1FFh to 200h. This interrupt provides the host with an early warning that the TxCOL counter should be read before it reaches 3FFh and starts over (by ...
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CS8900A Crystal LAN™ Ethernet Controller 2-partDefDis Before a transmission can begin, the CS8900A follows a deferral procedure. With the 2-part- DefDis bit clear, the CS8900A uses the standard two-part deferral as defined in ISO/IEC 8802- 3 paragraph 4.2.3.2.1. With the ...
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Register 15: Self Control (SelfCTL, Read/Write, Address: PacketPage base + 0114h RESET F E HCB1 HCB0 HC1E SelfCTL controls the operation of the LED outputs and the lower-power modes. 010101 These bits provide an internal address used ...
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CS8900A Crystal LAN™ Ethernet Controller 4.4.19 Register 16: Self Status (SelfST, Read-only, Address: PacketPage base + 0136h INITD 3.3V Active F E SelfST reports the status of the EEPROM interface and the initialization process. 010110 These bits provide ...
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ResetRxDMA When set, the RxDMA offset pointer at PacketPage base + 0026h is reset to zero. When the host sets this bit, the CS8900A does the following: 1.Terminates the current receive DMA activity, if any. 2.Clears all internal receive buffers. ...
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CS8900A Crystal LAN™ Ethernet Controller Register. When reading this register, these bits will be 011000, where the LSB corresponds to Bit 0. TxBidErr If set, the host has commanded the CS8900A to transmit a frame that the CS8900A will not ...
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Disable Backoff When set, the backoff algorithm is disabled. The CS8900A transmitter looks only for completion of the inter packet gap before starting transmission. When clear, the backoff algorithm is used. FDX When set, 10BASE-T full duplex mode is enabled ...
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CS8900A Crystal LAN™ Ethernet Controller 4.5 Initiate Transmit Registers 4.5.1 Transmit Command Request - TxCMD (Write-only, Address: PacketPage base + 0144h TxStart F E TxPadDis The word written to PacketPage base + 0144h tells the CS8900A how the ...
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CMD, the length of the transmitted frame is written into this register. The length of the transmitted frame may be modified by the configuration of the TxPadDis and InhibitCRC bits in the TxCMD register. See Table 36, and Section 5.6 ...
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CS8900A Crystal LAN™ Ethernet Controller 4.6 Address Filter Registers 4.6.1 Logical Address Filter (hash table) (Read/Write, Address: PacketPage base + 0150h) Address 0157h Address 0156h Address 0155h Address 0154h Address 0153h Address 0152h Address 0151h Address 0150h Most-signifi- cant byte ...
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Receive and Transmit Frame Locations The Receive and Transmit Frame PacketPage locations are used to transfer Ethernet frames to and from the host. The host sequentially writes to and reads from these locations, and internal buffer memory is dynamically ...
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CS8900A Crystal LAN™ Ethernet Controller byte address must be followed by a byte access to an odd-byte address before the host may execute a word access (this will realign the word transfers to even-byte boundaries). On the other hand, a ...
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The address on the ISA System Address bus (SA0 - SA19) is within the Memory space range of the CS8900A or Boot PROM. • The CHIPSEL input pin is low. • Either the MEMR pin or the MEMW pin ...
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CS8900A Crystal LAN™ Ethernet Controller can be written. If clear, the host must wait for CS8900A buffer memory to become available. If Rdy4TxiE (Register B, Buf- CFG, Bit 8) is set, the host will be interrupt- ed when Rdy4Tx (Register ...
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The Transmit Command tells the CS8900A that the host has a frame to be transmitted, as well as how that frame should be transmitted. This port is mapped into Pack- etPage base + 0144h. See Register 9 in Section ...
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CS8900A Crystal LAN™ Ethernet Controller base + 000Ch). If Rdy4TxNOW is set, the frame can be written. If clear, the host must wait for CS8900A buffer memory to be- come available. If Rdy4TxiE (Register B, BufCFG, Bit 8) is set, ...
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OPERATION 5.1 Managing Interrupts and Servicing the Interrupt Status Queue The Interrupt Status Queue (ISQ) is used by the CS8900A to communicate Event reports to the host processor. Whenever an event occurs that triggers an enabled CS8900A sets the ...
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CS8900A Crystal LAN™ Ethernet Controller An enabled interrupt occurs. The selected interrupt request pin is driven high (active) if not already high. The host reads the ISQ. The selected interrupt request pin is driven low. EXIT. Yes Interrupts re-enabled. (Interrupts ...
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Packet Received Preamble and Start-of-Frame Delimiter Removed Frame Pre- Processed Frame Temporarily Buffered No Use DMA? Frame Held Frame DMAed On Chip to Host Memory Host Reads Frame from CS8900A Memory Host Memory Figure 20. Frame Reception memory via host ...
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CS8900A Crystal LAN™ Ethernet Controller 5.2.2.1 Configuring the Physical Interface Configuring the physical interface consists of determining which Ethernet interface should be active, and enabling the receive logic for serial reception. This is done via the LineCTL register (Register 13) ...
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Register B, BufCFG Bit Bit Name Operation 7 RxDMAiE When set, there is an interrupt if one or more frames are trans- ferred via DMA. A RxMissiE When set, there is an interrupt if a frame is missed due to ...
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CS8900A Crystal LAN™ Ethernet Controller Receive Frame Destination Address Filter Check: - PromiscuousA? - IAHashA? - MulticastA? - IndividualA? - BroadcastA? Pass No DA Filter? Yes Generate Early Interrupts if Enabled (see next figure) Acceptance Filter Check: - RxOKA? - ...
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RxDest set. Host may read the DA (first 6 received bytes). Rx128 set and RxDest cleared. Host may read first 128 received bytes. 84 Receive Frame Yes No DA Filter Discard Frame Passed? Yes 64 bytes Received? No EOF No ...
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CS8900A Crystal LAN™ Ethernet Controller This section describes buffering and transfer- ring held receive frames. Section 5.3 on page 90 through Section 5.5 on page 96 de- scribe DMAed receive frames. 5.2.5 Buffering Held Receive Frames If space is available, ...
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Example of Memory Mode Receive Operation A common length for short frames is 64 bytes, including the 4-byte CRC. Suppose that such a frame has been received with the CS8900A configured as follows: • The BufferCRC bit (Register 3, ...
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CS8900A Crystal LAN™ Ethernet Controller register can be read to determine the final frame status. The sequence is as follows the start of a frame, the byte counter matches the incoming character counter. The byte counter will have ...
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The IAHashA, MulticastA, IndividualA, and BroadcastA bits are used independently result, many DA filter combinations are possi- ble. For example, if MulticastA and IndividualA are set, then all frames that are either Multicast IAHashA PromiscuousA MulticastA 0 0 ...
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CS8900A Crystal LAN™ Ethernet Controller 5.2.13 Broadcast Frame Hashing Excep- tion Table 26 describes in detail the content of the RxEvent register for each output of the hash and address filters, and describes an excep- tion to normal processing. That ...
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Address Erred Passes Type of Frame? Hash Received Filter? Frame Broad- no yes ExtraData Runt CRC Error Broadcast Individual Adr cast (Note 6) Address no yes ExtraData Runt CRC Error Broadcast Individual Adr (Note ExtraData Runt CRC ...
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CS8900A Crystal LAN™ Ethernet Controller PacketPage Register Description Address 0028h DMA Frame Count: The lower 12 bits define the number of valid frames transferred via DMA since the last read-out of this register. The upper 4 bits are reserved and ...
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Note that when in DMA mode, reading the con- tents of the RxEvent register will return 0000h. Status information should be obtained from the DMA buffer. 5.3.5 Committing Buffer Space to a DMAed Frame Although a receive frame may occupy ...
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CS8900A Crystal LAN™ Ethernet Controller be completely received. Usually, the DMA re- ceive frame interrupt (RxDMAiE, bit 7, Regis- ter B, BufCFG) is set so that the CS8900A generates an interrupt when a frame is trans- ferred by DMA. Figure ...
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Host Enters Interrupt Routine Read the DMA frame Count (C (PacketPage base + 0028h) 5.4 Auto-Switch DMA 5.4.1 Overview The CS8900A supports a unique feature, Auto-Switch DMA, that allows it to switch be- tween Memory or I/O mode and Receive ...
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CS8900A Crystal LAN™ Ethernet Controller ered as normal. If there isn't, the CS8900A's MAC engine compares the frame's Destina- tion Address (DA) to the criteria programmed into the DA filter. If the incoming DA fails the DA filter, the frame ...
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DMA channel. If this happens, the CS8900A will increment the RxMiss counter (Register 10) and clear any event reports (RxEvent and BufEvent) associated with ...
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CS8900A Crystal LAN™ Ethernet Controller Entering this example, the receive buffer is empty and the DMA Frame Count (PacketPage base + 0028h) is zero. Frame 1 received and completely stored in on-chip RAM. Frame 2 received and completely stored in ...
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DMA Start-of-Frame register (PacketPage base + 0026h); • updates the DMA Frame Count register (PacketPage base + 0028h); • updates DMA Byte Count register (Packet- Page base + 002Ah); • sets the RxDMAFrame bit (Register C, BufEvent, ...
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CS8900A Crystal LAN™ Ethernet Controller 5.5.6 Receive DMA Summary Table 30 summarize the Receive DMA config- uration options supported by the CS8900A. RxDMAonly AutoRxDMAiE (Register 3, (Register 3, (Register B, RxCFG,Bit 9) RxCFG, Bit A) BufCFG, Bit ...
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LineCTL register (Register 13) and is de- scribed in Table 31. Register 13, LineCTL Bit Bit Name Operation 7 SerTxON When set, transmission enabled. 8 AUIonly When set, AUI selected (takes precedence over AutoAUI/10BT). When clear, 10BASE-T selected. 9 ...
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CS8900A Crystal LAN™ Ethernet Controller 5.6.4 Enabling CRC Generation and Pad- ding Whenever the host issues a Transmit Request command, it must indicate whether or not the Cyclic Redundancy Check (CRC) value should be appended to the transmit frame, and ...
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The host bids for frame storage by writing the Transmit Command to the TxCMD reg- ister (memory base+ 0144h in memory mode and I/O base + 0004h in I/O mode). 2) The host writes the transmit frame length to ...
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CS8900A Crystal LAN™ Ethernet Controller Exit: can't Issue command Note: Issuing a command at this point will cause previous transmit frame to be lost. Figure 30. Transmit Operation in Polling Mode 5.6.8 Completing Transmission When the CS8900A successfully completes transmitting ...
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Exit: can't Issue command Note: Issuing a command at this point will cause previous transmit frame to be lost. Host Enters Interrupt Routine Host Reads ISQ No Rdy4Tx bit = 1? Process other events that caused interrupt 5.6.9 Rdy4TxNOW vs. ...
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CS8900A Crystal LAN™ Ethernet Controller not set). Also, the Rdy4Tx bit is used with in- terrupts and requires the Rdy4TxiE bit be set. Figure 30 provides a diagram of error free transmission without collision. 5.6.10 Committing Buffer Space to a ...
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CS8900A may not auto-select the 10BASE-T media. The cause of this situation is described in the following paragraphs. The original IEEE 802.3 specification requires the MAC to wait until 4 valid link-pulses are re- ceived before asserting Link-OK. Any time ...
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CS8900A Crystal LAN™ Ethernet Controller 6.0 TEST 6.1 TEST MODES 6.1.1 Loopback & Collision Diagnostic Tests Internal and external Loopback and Collision tests can be used to verify the CS8900A's functionality when configured 10BASE-T or AUI operation. 6.1.2 Internal Tests ...
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Boundary Scan Boundary Scan test mode provides an easy and efficient board-level test for verifying that the CS8900A has been installed properly. Boundary Scan will check to see if the orienta- tion of the chip is correct, and if ...
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CS8900A Crystal LAN™ Ethernet Controller Pin Name Pin # Pin Name DMACK1 14 IOR DMACK0 16 IOW SD08-SD15 27-24, 21-18 SD0 - SD7 65-68, 71-74 MEMW 28 RESET MEMR 29 SLEEP Table 41. (continued) The input pins not included in ...
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AEN switches high Figure 32. Boundary Scan Continuity Cycle 110 Not in Boundary Scan Test Mode TEST switches low (AEN must be low) ENTER BOUNDARY SCAN: CS8900A resets, all digital output pins and bi-directional pins enter High-Z state, and AEN ...
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CS8900A Crystal LAN™ Ethernet Controller TESTSEL AEN Outputs All outputs tri-state EEDataOut OUTPUTS Hi Z DS271F5 LINKLED LANLED BSTATUS low low low SLEEP OUTPUT TEST 34 Clocks COMPLETE CONTINUITY CYCLE 85 Clocks Figure 33. Boundary Scan Timing CIRRUS LOGIC PRODUCT ...
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CHARACTERISTICS/SPECIFICATIONS - COMMERCIAL 7.1 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Input Current Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature WARNING: Normal operation is not guaranteed at these extremes. 7.2 RECOMMENDED OPERATING CONDITIONS to 0 V.) Parameter ...
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CS8900A Crystal LAN™ Ethernet Controller DC CHARACTERISTICS Parameter Digital Inputs and Outputs Power Supply Current while Active 5.0V Power Supply Current while Active 3.3V Output Low Voltage ...
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SWITCHING CHARACTERISTICS Parameter 16-Bit I/O Read, IOCHRDY Not Used Address, AEN, SBHE active to IOCS16 low Address, AEN, SBHE active to IOR active IOR low to SD valid Address, AEN, SBHE hold after IOR inactive IOR inactive to active ...
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CS8900A Crystal LAN™ Ethernet Controller SWITCHING CHARACTERISTICS Parameter 16-Bit Memory Read, IOCHRDY Not Used SA [19:0], SBHE, CHIPSEL, active to MEMCS16 low Address, SBHE, CHIPSEL active to MEMR active MEMR low to SD valid Address, SBHE, CHIPSEL hold after MEMR ...
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SWITCHING CHARACTERISTICS Parameter DMA Read DMACKx active to IOR active AEN active to IOR active IOR active to Data Valid IOR inactive to SD 3-state IOR n-1 high to DMARQx inactive DMACKx, AEN hold after IOR high 16-Bit I/O Write ...
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CS8900A Crystal LAN™ Ethernet Controller SWITCHING CHARACTERISTICS Parameter 16-Bit Memory Write Address, SBHE, CHIPSEL valid to MEMCS16 low Address, SBHE, CHIPSEL valid to MEMW low MEMW pulse width MEMW low to SD valid SD hold after MEMW high Address hold ...
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SWITCHING CHARACTERISTICS Parameter 10BASE-T Receive Allowable Received Jitter at Bit Cell Center Allowable Received Jitter at Bit Cell Boundary Carrier Sense Assertion Delay Invalid Preamble Bits after Assertion of Carrier Sense Carrier Sense Deassertion Delay 10BASE-T Link Integrity First Transmitted ...
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CS8900A Crystal LAN™ Ethernet Controller SWITCHING CHARACTERISTICS Parameter AUI Transmit DO Pair Rise and Fall Times DO Pair Jitter at Bit Cell Center DO Pair Positive Hold Time at Start of Idle DO Pair Return to ≤ 40 mVp after ...
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SWITCHING CHARACTERISTICS Parameter External Boot PROM Access Address active to MEMR MEMR active to CSOUT low MEMR inactive to CSOUT high EEPROM EESK Setup time relative to EECS EECS/ELCS_b Setup time wrt ↑ EESK EEDataOut Setup time wrt ↑ EESK ...
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CS8900A Crystal LAN™ Ethernet Controller 7.5 10BASE-T WIRING CS8900A Rt TXD + TXD - Rt RXD+ + 0.01 μ F RXD- - • center tap transformer is used on the RXD+ and RXD- inputs, replace the pair of ...
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AUI WIRING CS8900A 0.01 uF Col 0. 7.7 QUARTZ CRYSTAL REQUIREMENTS lowing specifications) Parameter Parallel Resonant Frequency Resonant Frequency Error ...
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CS8900A Crystal LAN™ Ethernet Controller 8.0 CHARACTERISTICS/SPECIFICATIONS - INDUSTRIAL 8.1 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Input Current Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature WARNING: Normal operation is not guaranteed at these extremes. 8.2 RECOMMENDED OPERATING ...
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DC CHARACTERISTICS Parameter Digital Inputs and Outputs Power Supply Current while Active 5.0V Power Supply Current while Active 3.3V Output Low Voltage Output Low Voltage ...
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CS8900A Crystal LAN™ Ethernet Controller 8.4 SWITCHING CHARACTERISTICS Parameter 16-Bit I/O Read, IOCHRDY Not Used Address, AEN, SBHE active to IOCS16 low Address, AEN, SBHE active to IOR active IOR low to SD valid Address, AEN, SBHE hold after IOR ...
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SWITCHING CHARACTERISTICS Parameter 16-Bit Memory Read, IOCHRDY Not Used SA [19:0], SBHE, CHIPSEL, active to MEMCS16 low Address, SBHE, CHIPSEL active to MEMR active MEMR low to SD valid Address, SBHE, CHIPSEL hold after MEMR inactive MEMR inactive to SD ...
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CS8900A Crystal LAN™ Ethernet Controller SWITCHING CHARACTERISTICS Parameter DMA Read DMACKx active to IOR active AEN active to IOR active IOR active to Data Valid IOR inactive to SD 3-state IOR n-1 high to DMARQx inactive DMACKx, AEN hold after ...
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SWITCHING CHARACTERISTICS Parameter 16-Bit Memory Write Address, SBHE, CHIPSEL valid to MEMCS16 low Address, SBHE, CHIPSEL valid to MEMW low MEMW pulse width MEMW low to SD valid SD hold after MEMW high Address hold after MEMW inactive MEMW inactive ...
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CS8900A Crystal LAN™ Ethernet Controller SWITCHING CHARACTERISTICS Parameter 10BASE-T Receive Allowable Received Jitter at Bit Cell Center Allowable Received Jitter at Bit Cell Boundary Carrier Sense Assertion Delay Invalid Preamble Bits after Assertion of Carrier Sense Carrier Sense Deassertion Delay ...
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SWITCHING CHARACTERISTICS Parameter AUI Transmit DO Pair Rise and Fall Times DO Pair Jitter at Bit Cell Center DO Pair Positive Hold Time at Start of Idle DO Pair Return to ≤ 40 mVp after Last Positive Transition AUI Receive ...
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CS8900A Crystal LAN™ Ethernet Controller SWITCHING CHARACTERISTICS Parameter External Boot PROM Access Address active to MEMR MEMR active to CSOUT low MEMR inactive to CSOUT high EEPROM EESK Setup time relative to EECS EECS/ELCS_b Setup time wrt ↑ EESK EEDataOut ...
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WIRING CS8900A Rt TXD + TXD - Rt RXD+ + 0.01 μ F RXD- - • center tap transformer is used on the RXD+ and RXD- inputs, replace the pair of Rr re- sistors with a ...
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CS8900A Crystal LAN™ Ethernet Controller 8.6 AUI WIRING CS8900A Col 8.7 QUARTZ CRYSTAL REQUIREMENTS lowing specifications) Parameter Parallel Resonant Frequency Resonant Frequency ...
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PHYSICAL DIMENSIONS 100L LQFP PACKAGE DRAWING D D1 ∝ Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 134 MILLIMETERS DIM MIN A --- A1 0.05 B 0.17 ...
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CS8900A Crystal LAN™ Ethernet Controller 10.0 GLOSSARY OF TERMS 10.1 Acronyms AUI Attachment Unit Interface CRC Cyclic Redundancy Check CS Carrier Sense CSMA/CD Carrier Sense Multiple Access with Collision Detection DA Destination Address EEPROM Electrically Erasable Programmable Read Only Memory ...
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Definitions Cyclic Redundancy Check The method used to compute the 32-bit frame check sequence (FCS). Frame Check Sequence The 32-bit field at the end of a frame that contains the result of the cyclic redundancy check (CRC). Frame An ...
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CS8900A Crystal LAN™ Ethernet Controller 10.3 Acronyms Specific to the CS8900A BufCFG BufEvent BusCTL BusST ENDEC ISQ LineCTL LineST RxCFG RxCTL RxEvent SelfCTL SelfST TestCTL TxCFG TxCMD TxEvent 10.4 Definitions Specific to the CS8900A Act-Once bit A control bit that ...
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Standby A feature of the CS8900A used to conserve power. When in Standby mode, the CS8900A can be awakened either by 10BASE-T activity or host command. Suspend A feature of the CS8900A used to conserve power. When in Suspend mode, ...