DP83848I-MAU-EK National Semiconductor, DP83848I-MAU-EK Datasheet - Page 34

• Manufacturer Part Number: DP83848I-MAU-EK
• Description: BOARD EVALUATION DP83848I
• Manufacturer: National Semiconductor

Specifications of DP83848I-MAU-EK

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: DP83848I
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

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5.2 ESD Protection
Typically, ESD precautions are predominantly in effect
when handling the devices or board before being installed
in a system. In those cases, strict handling procedures
need be implemented during the manufacturing process to
greatly reduce the occurrences of catastrophic ESD
events. After the system is assembled, internal compo-
nents are less sensitive from ESD events.
See Section 8.0 for ESD rating.
5.3 Clock In (X1) Requirements
The DP83848I supports an external CMOS level oscillator
source or a crystal resonator device.
Oscillator
If an external clock source is used, X1 should be tied to the
clock source and X2 should be left floating.
Specifications for CMOS oscillators: 25 MHz in MII Mode
and 50 MHz in RMII Mode are listed in Table 7 and Table 8.
Crystal
A 25 MHz, parallel, 20 pF load crystal resonator should be
used if a crystal source is desired. Figure 12 shows a typi-
cal connection for a crystal resonator circuit. The load
1
This limit is provided as a guideline for component selection and to guaranteed by production testing.
Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance.
Rise / Fall Time
Parameter
Frequency
Frequency
Frequency
Symmetry
Tolerance
Stability
Jitter
Jitter
40%
Min
Table 7. 25 MHz Oscillator Specification
Typ
25
Table 6.
34
capacitor values will vary with the crystal vendors; check
with the vendor for the recommended loads.
The oscillator circuit is designed to drive a parallel reso-
nance AT cut crystal with a minimum drive level of 100 W
and a maximum of 500 W. If a crystal is specified for a
lower drive level, a current limiting resistor should be
placed in series between X2 and the crystal.
As a starting point for evaluating an oscillator circuit, if the
requirements for the crystal are not known, C
should be set at 33 pF, and R
Specification for 25 MHz crystal are listed in Table 9.
800
800
Max
60%
+50
+50
6
1
1
Figure 12. Crystal Oscillator Circuit
C
L1
X1
Units
nsec
psec
psec
MHz
ppm
ppm
1
should be set at 0
Operational Temperature
1 year aging
20% - 80%
Duty Cycle
Condition
Short term
Long term
X2
R
C
1
L2
L1
and C
L2