ISL6142/52EVAL1 Intersil, ISL6142/52EVAL1 Datasheet - Page 5

• Manufacturer Part Number: ISL6142/52EVAL1
• Description: EVAL BOARD W/CURRENT MONITOR
• Manufacturer: Intersil

Specifications of ISL6142/52EVAL1

• Main Purpose: Power Management, Hot Swap Controller
• Utilized Ic / Part: ISL6142, 6152
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

Current Monitoring
The ISL6142/52 has a unique feature that monitors and
reports the current flowing through the R1 sense resistor
(I
scaled version of that current is sourced from the IS
to -V
conversion. The IS
an A to D converter to provide the system real time load/fault
current up-dates. The IS
the resistor ratio R1/R7. The scale factor for channel A is
0.270Ω/270Ω = 0.001, so IS
to -V
With R9 set to 10KΩ, the voltage on the IS
3. Disconnect the BUS board from the CONTROL/LOAD
4. Disconnect the BUS/CONTROL from the LOAD; now
SENSE
Current threshold of 185mA (0.05V/0.27ohm = 185 mA).
The FET should turn off, the A/B ON LED should go off,
the fault LED’s D5B and D6B should both turn on. For the
ISL6152, D6A will turn on (D5A will always be on). The
Over-Current Time-Out is programmable with the C3
capacitor and is set to approximately 600uS. The
response is easily monitored with an oscilloscope;
connect voltage probes to the GATE and IS
initiate the Over-Current event. The GATE pin will be
pulled low (
the programmed time-out period. If the fault persists, the
GATE will be pulled to -V
user may also want to monitor the load current during this
event with a current probe. Load current measurements
and the current monitor output (IS
greater detail in the Current Monitor section. To return to
normal operation, un-switch both load resistors, press
and release SW1 or toggle SW2 to +5V and back to -V
This clears the Over-Current latch and initiates a normal
start-up.
boards; now plug it back in; this simulates a hot plug
board being inserted into a live connector. The FETs
should turn on in a controlled manner, based on the gate
timing components. If a load capacitor is added, the user
may have to reduce the value of R1 to ensure the Over-
Current trip point is not exceeded by the inrush current;
or increase the value of C2 to keep the inrush current
below the Over-Current threshold. Equation #1 shows
the relationship between C2, the load capacitor (C
the inrush current, where I
(50uA nominal). The Over-Current trip point (I
defined in equation #2. Reference the ISL6142/52 data
sheet for more detailed information regarding component
selection.
plug it back in; this simulates a load being plugged into a
powered motherboard with hot plug protection.
I
I
IN
IN
inrush
OC
) for each milli-amp of current flowing through R1.
through resistor R9, providing a current to voltage
). The IS+ and IS- pins sense the load current. A
=
------------------- -
R
=
50mv
sense
I
PU
∼
4V) to limit the current to 50mV/R
×
OUT
C
------ -
C
L
2
pin will typically be tied to the input of
OUT
OUT
/ I
IN
5
PU
SENSE
and the FET will turn off. The
will source 1uA (through R9
is the gate pull-up current
OUT
scaling factor is set by
) are discussed in
OUT
OUT
pin will
OC
SENSE
(EQ. 1)
(EQ. 2)
pins and
OUT
) is
L
) and
pin
for
IN
.
equate to 10mv for each milli-amp of load current. The
current scaling factor for channel B (0.000985) is slightly
less than that of channel A, as the standard value for the
R7/R8 through-hole resistor is 274Ω. To keep the current to
voltage scaling factors of the two channels equal, the value
of R9B (10.2KΩ) is set slightly higher. With these component
values the output voltage to load current ratio is
10.05mV/1.0mA. The current scaling factor is easy to alter
on channel B with the through-hole components. If the value
of R7 is changed, keep in mind that R8 should match as
closely as possible to minimize the error of the current
monitor circuit. A match of 1% or better is recommended.
There are several ways to measure the actual load current,
as one might be interested in examining the correlation
between it and the current monitor output. A voltmeter can
be placed across the R1 sense resistor and the current can
be calculated (I = V/R; R = 0.27 ohms). However, for a more
for accurate measurement and the ability to examine current
transients, a current probe connected to an oscilloscope is
recommended. First, place all of the load switches in the “No
Load” position (up). Connect a wire loop from -VOUTA/B to
an external load and then back to GND. There are also a set
of connector posts for each channel located next to the
FET’s which provide the same capability. Each channel has
a post that connects to ground (TPLD1A - channel A,
TPLD1B - channel B) and a post that connects to -VOUTA/B
(TPLD2A - channel A, TPLD2B - channel B). The load
resistors can also be used by connecting the wire loop from
the output to one of the load resistor terminals closest to the
switch. Now the load current will flow through the wire loop,
and can be monitored.
Logic Inputs/Outputs
The Logic levels used to drive the DIS input must be
referenced to the negative supply rail (-V
(<1.5V) will allow the GATE pin to be pulled high and turn on
the FET if no fault conditions are present; A logic high
(>3.0V) will pull the GATE pin low and turn off the FET.
Toggling the pin high and then low will also reset the Over-
Current latch if it has been set. The logic levels are applied
to the pin with the SW2A/B switch. When the switch is in the
up position the DIS pin is connected to -V
down position the DIS pin connects to the +5VA/B test pins
to produce a logic high). These test pins (red) must be
physically connected to the external +5V supply (PS2).
Jumpers JP2A/B are provided to allow the user to by-pass
the switch and drive the DIS pin externally (TP3 or post of
JP2). Also note that a weak internal pull-up device will pull
the pin high to an internal +5V rail, creating a logic high if the
pin is left open.
The FAULT output is an open-drain, pull-down device
referenced to V
Current latch is set. It goes to a high impedance state when
the fault latch is reset by toggling the UV or DIS pins. The
pull-up resistor (R10) is connected to the +5VA/B test pin
EE
. It is pulled active low whenever the Over-
IN
IN
). A logic low
(logic low); in the