KIT33984PNAEVB Freescale Semiconductor, KIT33984PNAEVB Datasheet - Page 24

• Manufacturer Part Number: KIT33984PNAEVB
• Description: KIT PRELIM EVALUATION MC3398PNA
• Manufacturer: Freescale Semiconductor
• Type: Other Power Managementr

Specifications of KIT33984PNAEVB

• Main Purpose: Power Management, High Side Driver (Internal FET)
• Embedded: No
• Utilized Ic / Part: MC33984
• Primary Attributes: Output current monitoring, 2 SPI-selectable current ratios
• Secondary Attributes: SPI control of over-current limit, open load detection, output ON/OFF, slew rates
• Input Voltage: 6 V to 27 V
• Interface Type: SPI
• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MC33984

SERIAL INPUT COMMUNICATION
messages. A message is transmitted by the MCU starting
with the MSB, D7, and ending with the LSB, D0
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB (D7)
is the watchdog bit and in some cases a register address bit
common to both outputs or specific to an output; the next
three bits, D6 : D4, are used to select the command register;
and the remaining four bits, D3 : D0, are used to configure and
control the outputs and their protection features.
accommodate those applications where daisy chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of eight bits. Any attempt made to
latch in a message that is not eight bits will be ignored.
configure the device and to control the state of the output.
Table
addressed via D6 : D4 of the incoming SPI word
Table 9. SI Message Bit Assignment
24
33984
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Bit Sig SI Msg Bit
MSB
LSB
C S B
S C L K
SPI communication is accomplished using 8-bit
Multiple messages can be transmitted in succession to
The 33984 has defined registers, which are used to
CS
SI
SCLK
S O
SO
S I
N O T E S :
Notes
10, summarizes the SI registers. The registers are
D6 : D4
D3 : D1
1.
2. D7:D0 relate to the most recent ordered entry of data into the device.
3. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.
4. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
D 7
1 .
2 .
3 .
4 .
D7
D0
O D 7
RST
R S T
R S T B
D 0 , D 1 , D 2 , . . . , a n d D 7 r e l a t e t o t h e m o s t r e c e n t o r d e r e d e n t r y o f d a t a i n t o t h e S P S S
O D 0 , O D 1 , O D 2 , . . . , a n d O D 7 r e l a t e t o t h e f i r s t 8 b i t s o f o r d e r e d f a u l t a n d s t a t u s d a t a o u t o f t h e d e v i c e .
O D 0 , O D 1 , O D 2 , . . . , a n d O D 7 r e p r e s e n t t h e f i r s t 8 b i t s o f o r d e r e d f a u l t a n d s t a t u s d a t a o u t o f t h e S P S S
is a Logic [1] state during the above operation.
D 6
O D 6
Register address bit for output selection.
Also used for watchdog: toggled to satisfy
watchdog requirements.
Register address bits.
Used to configure the inputs, outputs, and
the device protection features and SO status
content.
Used to configure the inputs, outputs, and
the device protection features and SO status
content.
i s i n a l o g i c 1 s t a t e d u r i n g t h e a b o v e o p e r a t i o n .
D 5
O D 5
Message Bit Description
F I G U R E
Figure 10. Multiple 8-Bit Word SPI Communication
4 b .
D 2
O D 2
M U L T I P L E
(Table
(Table
D 1
O D 1
9).
9).
D 0
8 b i t W O R D
O D 0
D 7 *
Table 10. Serial Input Address and Configuration Bit
SOCHLR s
CDTOLR s
Register
D 7
STATR
x = Don’t care.
s (SOA3 bit) = Selection of output: Logic [0] = HS0, Logic [1] =
HS1.
OSDR
UOVR
TEST
DICR
WDR
OCR
NAR
SI
D 6 *
S P I C O M M U N I C A T I O N
D 6
D7 D6 D5 D4
s
x
s
0
1
0
1
x
Map
D 5 *
D 5
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
1
Analog Integrated Circuit Device Data
OL_DIS
CSNS1
SOCHs SOCL2s SOCL1s SOCL0s
FAST
Serial Input Data
SR s
D3
EN
0
0
0
0
0
s
Freescale Internal Use (Test)
D 2 *
IN1_SPI CSNS0
CD_DIS
Freescale Semiconductor
D 2
SOA2
CSNS
high s
OSD2
D2
s
0
0
0
D 1 *
D 1
OCLT1s OCLT0 s
IN DIS s
UV_dis OV_dis
SOA1
OSD1
WD1
D 0 *
D1
EN
0
D 0
IN0_SPI
OSD0
SOA0
A/Os
WD0
D0
0